From: Tom Rini <trini@kernel.crashing.org>
To: Paul Mackerras <paulus@samba.org>
Cc: Dan Malek <dan@embeddededge.com>,
David Gibson <david@gibson.dropbear.id.au>,
linuxppc-embedded@lists.linuxppc.org
Subject: Re: LMBench and CONFIG_PIN_TLB
Date: Wed, 29 May 2002 16:16:00 -0700 [thread overview]
Message-ID: <20020529231600.GW5997@opus.bloom.county> (raw)
In-Reply-To: <15605.24191.948013.249297@argo.ozlabs.ibm.com>
On Thu, May 30, 2002 at 09:04:31AM +1000, Paul Mackerras wrote:
> available. Tom Rini mentioned the other day that some 8xx processors
> only have 8 (I assume he meant 8 data + 8 instruction).
Quite probably, yes. :)
[snip]
> processor, which has 64. I don't think he was advocating removing the
> config option on the 8xx processors (actually, why is there the "860
> only" comment in there?)
Because the current code goes and pins 8 or so TLBs (4 data, 4
instruction) which won't fly on the ones which only allow for 2/8 to be
pinned. So 860 is a slight mislabing, if I read it all correctly.
--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2002-05-29 23:16 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-05-29 3:08 LMBench and CONFIG_PIN_TLB David Gibson
2002-05-29 14:40 ` Dan Malek
2002-05-29 23:04 ` Paul Mackerras
2002-05-29 23:16 ` Tom Rini [this message]
2002-05-30 1:34 ` Dan Malek
2002-05-30 5:14 ` David Gibson
2002-05-30 16:09 ` Matthew Locke
2002-05-30 23:50 ` Paul Mackerras
2002-05-30 23:01 ` Matthew Locke
2002-05-31 2:39 ` David Gibson
2002-05-31 0:10 ` Tom Rini
2002-05-31 14:48 ` Tom Rini
2002-05-30 5:05 ` David Gibson
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