Re: interrupt latency

[Mark Hapke <mah@tzi.de>]

Hello,
thanks for your answer!

I am aware of the fact that this issue depends completely on the equipment 
used, as well on the load of the concerned bus systems etc. I actually need 
some information of that sort to mention in my diploma thesis, so I don't 
have to really quantify the microsconds consumed, although the points listed 
below are still interesting.
It is not so important, whether the latency is about 10 microseconds or 11, I 
only need some approximation and I appreciate any hint.

Thanks,
Mark

> You need a fast timer that sees the IRQ raise and is read in the IRQ
> handler to measure it easily. Be aware that the apic bus is message
> based so the apic worst case times on PIII at least are an order of
> magnitude above average. Furthermore on a PC your instruction fetch for
> the first instruction of the IRQ handler might end up triggering ITLB,
> DTLB fetches which in turn have to fetch a page directory and a page
> table each from main memory and then an additional line fetched for the
> code itself.
>
> If you think that is getting complicated each of the memory accesses may
> in turn collide with other bus traffic (invalidates, memory writes by
> other masters or processors) and so forth.
>
> Your processor might be running at varying speeds (including thermal
> events).
>
> Finally your processor may be stalled on a PCI space access when the IRQ
> arrives. That on some badly behaved graphics cards can push your IRQ
> response up near the millisecond level.
>
> You need to define your entire system very carefully before you can
> answer the question for PC class systems.