From: Ralf Baechle <ralf@oss.sgi.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>
Cc: Carsten Langgaard <carstenl@mips.com>,
linux-mips@fnet.fr, linux-mips@oss.sgi.com
Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards
Date: Wed, 31 Jul 2002 22:31:58 +0200 [thread overview]
Message-ID: <20020731223158.A6394@dea.linux-mips.net> (raw)
In-Reply-To: <Pine.GSO.3.96.1020731133006.10088A-100000@delta.ds2.pg.gda.pl>; from macro@ds2.pg.gda.pl on Wed, Jul 31, 2002 at 01:34:17PM +0200
On Wed, Jul 31, 2002 at 01:34:17PM +0200, Maciej W. Rozycki wrote:
> > Nope, on R4000 four cycles are needed between the tlbwr and a eret
> > instruction; on the R4600 just two.
>
> Ugh, I missed this entirely, thanks for pointing it out. The doc implies
> three cycles for the R4000 actually, though.
I doublechecked the docs for the R4700 as well - just one cycle needed
between a tlbw and eret.
Ralf
next prev parent reply other threads:[~2002-07-31 20:30 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-07-29 15:23 [patch] MIPS64 R4k TLB refill CP0 hazards Maciej W. Rozycki
2002-07-29 20:10 ` Carsten Langgaard
2002-07-30 6:59 ` Carsten Langgaard
2002-07-30 11:29 ` Ralf Baechle
2002-07-30 12:09 ` Carsten Langgaard
2002-07-30 12:44 ` Maciej W. Rozycki
2002-07-30 22:47 ` Ralf Baechle
2002-07-31 11:34 ` Maciej W. Rozycki
2002-07-31 20:31 ` Ralf Baechle [this message]
2002-08-01 15:24 ` Maciej W. Rozycki
2002-08-01 17:18 ` Ralf Baechle
2002-08-02 9:32 ` Carsten Langgaard
2002-08-02 11:05 ` Ralf Baechle
2002-08-02 11:09 ` Carsten Langgaard
2002-07-30 12:39 ` Kevin D. Kissell
2002-07-30 12:39 ` Kevin D. Kissell
2002-07-31 2:05 ` Ralf Baechle
2002-07-31 7:28 ` Kevin D. Kissell
2002-07-31 7:28 ` Kevin D. Kissell
2002-07-31 11:49 ` Maciej W. Rozycki
2002-07-31 18:22 ` Ralf Baechle
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