From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id ; Thu, 8 Aug 2002 11:41:40 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id ; Thu, 8 Aug 2002 11:41:40 -0400 Received: from pizda.ninka.net ([216.101.162.242]:21731 "EHLO pizda.ninka.net") by vger.kernel.org with ESMTP id ; Thu, 8 Aug 2002 11:41:40 -0400 Date: Thu, 08 Aug 2002 08:32:15 -0700 (PDT) Message-Id: <20020808.083215.41828271.davem@redhat.com> To: rkuhn@e18.physik.tu-muenchen.de Cc: kwijibo@zianet.com, linux-kernel@vger.kernel.org Subject: Re: kernel BUG at tg3.c:1557 From: "David S. Miller" In-Reply-To: References: X-Mailer: Mew version 2.1 on Emacs 21.1 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org From: Roland Kuhn Date: Thu, 8 Aug 2002 14:39:56 +0200 (CEST) If I can do more to help sort this out, please tell me. With my fix to prefix every write with a dummy read, the system is rock solid, not a single glitch on 12 machines in the last 14 hours. I'll figure out why this indirect register stuff isn't working. I'm very curious on how this all works, so would somebody please give me a pointer where to start reading concerning linux and PCI reordering/pci_write_config_dword? The PCI controller might be illegally reordering PCI MEM space accesses to the card's registers with asynchronous DMA activity. If that is true, the explanation is that the PCI config space accesses synchrnoize wrt. pending DMA operations the device is doing.