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From: Anton Blanchard <anton@samba.org>
To: Peter Bergner <bergner@borg.umn.edu>
Cc: Paul Mackerras <paulus@samba.org>,
	linuxPPC Dev <linuxppc-dev@lists.linuxppc.org>,
	Mike Corrigan <mikejc@us.ibm.com>
Subject: Re: FP save/restore code in ppc32/ppc64 kernels
Date: Thu, 8 Aug 2002 23:18:33 +1000	[thread overview]
Message-ID: <20020808131833.GD23964@krispykreme> (raw)
In-Reply-To: <20020808114646.GA23964@krispykreme>



> The final thing to look at is what ptrace returns for the MSR. I
> suggested that we should copy in the FE0/FE1 bits out of the thread
> struct (since the MSR_FP, FE0 and FE1 bits will always be zero as
> ptrace does a giveup_fpu just before reading any FP stuff). Paul
> pointed out for completeness we should always set the MSR_FP bit too.

To follow up, this is what we currently see via ptrace:

./msr
msr = d032

And here is what we see with the above fixes:

./msr
msr = f932

fpemode is a small program from Paulus that changes the FE0 and
FE1 bits via the prctl. This shows:

./fpemode 0 ./msr
msr = f032

./fpemode 1 ./msr
msr = f132

./fpemode 2 ./msr
msr = f832

./fpemode 3 ./msr
msr = f932

Anton

** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

  reply	other threads:[~2002-08-08 13:18 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2002-08-07 16:23 FP save/restore code in ppc32/ppc64 kernels Peter Bergner
2002-08-08 11:46 ` Anton Blanchard
2002-08-08 13:18   ` Anton Blanchard [this message]
  -- strict thread matches above, loose matches on Subject: below --
2002-08-08 14:01 Mike Corrigan
2002-08-08 22:34 ` Paul Mackerras
2002-08-09  2:09   ` Peter Bergner
2002-08-12  2:38     ` Paul Mackerras
2002-08-12 14:34       ` Peter Bergner
2002-08-14  2:20         ` Peter Bergner

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