Re: L1_CACHE_SHIFT value for P4 ?

[Dave Jones <davej@codemonkey.org.uk>]

On Thu, Nov 21, 2002 at 02:42:50PM +0100, Andi Kleen wrote:

 > http://developer.intel.com/technology/itj/q12001/articles/art_2.htm
 > -> "Netburst microarchitecture" -> Level 2 Instruction and Data Cache
 > "The L2 cache is organized as an 8-way set-associative cache with 128 bytes 
 > per cache line. These 128-byte cache lines consist of two 64-byte sectors. 
 > A miss in the L2 cache typically initiates two 64-byte access requests to the 
 > system bus to fill both halves of the cache line.

Ok, this makes more sense. (and sounds familiar -- probably the same
thing I was pointed to last time this came up)
 
 > It is refering to the older 256K cached P4, but I doubt they changed it.
 > Your cache reporting may refer to the 64byte sectors or is just wrong

I think its counting just the sector. It certainly makes sense.

 > (would not be the first time that has happened - some P4 versions also
 > misreported their TLB size) 

Interesting. I should go read the errata so x86info handles that correctly..

 > For cache colouring purposes you need to use the 128 byte unit.

Agreed.

		Dave

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| Dave Jones.        http://www.codemonkey.org.uk
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