Re: unaligned load in branch delay slot

[Ralf Baechle <ralf@linux-mips.org>]

On Tue, Jan 28, 2003 at 10:30:20AM +0100, Geert Uytterhoeven wrote:

> If it happens, I should get a SIGILL, right?

Right.

Hmm...  If you can't reproduce this anymore I guess we should pull this
patch again?  Despite Mike basically acknowledging that such behaviour
exists I don't feel to well about applying patches for non-reproducable
processor behaviour and would rather prefer to wait until we believe to
know the full details.

?

> > +	set_fs(seg);
> 
> `seg' is never initialized?

Yep ...

> > +	case bcond_op:
> > +	case j_op:
> > +	case jal_op:
> > +	case beq_op:
> > +	case bne_op:
> > +	case blez_op:
> > +	case bgtz_op:
> > +	case beql_op:
> > +	case bnel_op:
> > +	case blezl_op:
> > +	case bgtzl_op:
> > +	case jalx_op:
> > +		return 1;	
> 
> I think you can remove the unconditional jumps, cfr. Mike's comments.

That's one of the points where I felt a bit unsafe about the extend of
the issue so I left the jumps in.  Anyway, why should it make a difference
if an instruction is conditional or not?

> Isn't the Vr4120A core MIPS32?

Vr4120 is MIPS III.

  Ralf