From: Dave Jones <davej@codemonkey.org.uk>
To: Paul Rolland <rol@as2917.net>
Cc: "'Juha Poutiainen'" <pode@iki.fi>, linux-kernel@vger.kernel.org
Subject: Re: L2 cache detection in Celeron 2GHz (P4 based)
Date: Wed, 19 Mar 2003 13:58:41 +0000 [thread overview]
Message-ID: <20030319135841.GC28770@suse.de> (raw)
In-Reply-To: <00b801c2edf0$105d7750$6100a8c0@witbe>
On Wed, Mar 19, 2003 at 09:18:04AM +0100, Paul Rolland wrote:
> You can also add that the L1 detection doesn't seem to be correct
> either :
> 0K Instruction cache, and 8K data cache for L1... This is not much
> for instruction, it seems it should be 12K...
That should be fixed in recent 2.4s (and not-so-recent 2.5s).
What version are you seeing this problem on?
Dave
next prev parent reply other threads:[~2003-03-19 13:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-03-19 6:47 L2 cache detection in Celeron 2GHz (P4 based) Juha Poutiainen
2003-03-19 8:18 ` Paul Rolland
2003-03-19 13:58 ` Dave Jones [this message]
2003-03-19 16:53 ` Paul Rolland
2003-03-19 17:01 ` Dave Jones
2003-03-19 13:53 ` Dave Jones
2003-03-19 17:53 ` Juha Poutiainen
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