From: Ralf Baechle <ralf@linux-mips.org>
To: Brian Murphy <brm@murphy.dk>
Cc: linux-mips@linux-mips.org
Subject: Re: [PATCH 2.4] trivial secondary cache probe fix for R5000/NEVADA
Date: Sun, 13 Apr 2003 21:15:31 +0200 [thread overview]
Message-ID: <20030413211531.A5000@linux-mips.org> (raw)
In-Reply-To: <E194mQF-0004aB-00@brian.localnet>; from brm@murphy.dk on Sun, Apr 13, 2003 at 08:41:47PM +0200
On Sun, Apr 13, 2003 at 08:41:47PM +0200, Brian Murphy wrote:
> despite the comment there are at least two more processors this
> probe is needed/works for.
I don't think we want to use this frightening jewel for more than necessary.
On the R5000 the secondary cache can nicely be probed by looking at the
c0_config register. c0_config.sc=0 indicates a second level cache is
present, setting the se bit in the same register enables it and the two
ss bits contain the size - doesn't that sound so much nicer than the
insane fragile stunt necessary for the R4000?
Ralf
prev parent reply other threads:[~2003-04-13 19:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-04-13 18:41 [PATCH 2.4] trivial secondary cache probe fix for R5000/NEVADA Brian Murphy
2003-04-13 19:15 ` Ralf Baechle [this message]
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