From: Ralf Baechle <ralf@linux-mips.org>
To: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org, Atsushi Nemoto <nemoto@toshiba-tops.co.jp>
Subject: Re: End c-tx49.c's misserable existence
Date: Mon, 14 Apr 2003 05:50:38 +0200 [thread overview]
Message-ID: <20030414055038.A29923@linux-mips.org> (raw)
In-Reply-To: <20030414.123514.74756574.nemoto@toshiba-tops.co.jp>; from anemo@mba.ocn.ne.jp on Mon, Apr 14, 2003 at 12:35:14PM +0900
On Mon, Apr 14, 2003 at 12:35:14PM +0900, Atsushi Nemoto wrote:
> TOSHIBA_ICACHE_WAR can be removed. This workaround is not needed
> if kernel does not modify the cache codes itself in run-time.
>
> When I wrote c-tx49.c I blindly followed the statement in TX49/H2
> manual's statement. ("If the instruction (i.e. CACHE) is issued for
> the line which this instruction itself exists, the following operation
> is not guaranteed.") Now I know this warning is only for
> self-modified code. There must be no problem if the codes is not
> modified in run-time. So please remove all TOSHIBA_ICACHE_WAR stuff
> and make c-r4k.c more clean.
Excellent. This should provide a good performance boost for the TX49
also as disabling the I-cache during the flush made the operation even
slower than it has to be.
Ralf
next prev parent reply other threads:[~2003-04-14 3:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20030412163215Z8225197-1272+1264@linux-mips.org>
2003-04-14 3:35 ` End c-tx49.c's misserable existence Atsushi Nemoto
2003-04-14 3:50 ` Ralf Baechle [this message]
2003-04-14 6:29 ` Atsushi Nemoto
2003-04-14 12:47 ` Maciej W. Rozycki
2003-04-14 15:48 ` Ralf Baechle
2003-04-15 15:15 ` Atsushi Nemoto
2003-04-15 15:19 ` Ralf Baechle
2003-08-01 13:27 ` Atsushi Nemoto
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