From: Jun Sun <jsun@mvista.com>
To: Steven Seeger <sseeger@stellartec.com>
Cc: linux-mips@linux-mips.org, jsun@mvista.com
Subject: Re: wait on vr4181 part 2
Date: Mon, 28 Apr 2003 10:24:21 -0700 [thread overview]
Message-ID: <20030428102421.A29907@mvista.com> (raw)
In-Reply-To: <089f01c30da9$e237d5d0$3501a8c0@wssseeger>; from sseeger@stellartec.com on Mon, Apr 28, 2003 at 10:16:18AM -0700
On Mon, Apr 28, 2003 at 10:16:18AM -0700, Steven Seeger wrote:
> If there is no wait, then what's that in arch/mips/vr4181/osprey/reset.c ?
Simple - it is a bug. :)
I got a confirmation from NEC that Vr4181 does _not_ have wait instruction.
It should generate an exception though.
In the halt case, kernel is probably in such a zombie state that we
don't even see the exception.
Jun
> void nec_osprey_halt(void)
> {
> printk("KERN_NOTICE "\n** You can safely turn off the power.\n");
> while(1)
> __asm__(".set\tmips3\n\t"
> "wait\n\t"
> ".set\tmips0");
> }
>
> Steve
>
next prev parent reply other threads:[~2003-04-28 17:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-04-28 16:25 crosscompile doesn't work :( Gabor Kerenyi
2003-04-28 17:16 ` wait on vr4181 part 2 Steven Seeger
2003-04-28 17:16 ` Steven Seeger
2003-04-28 17:24 ` Jun Sun [this message]
2003-04-28 19:47 ` crosscompile doesn't work :( Jeff Baitis
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