Re: Cpufreq: powernow-k7 weirdness

[Michael Frank <mflt1@micrologica.com.hk>]

On Monday 07 July 2003 21:12, Ducrot Bruno wrote:
> > The actual minimum time between steps depends on systems design and can
> > only be established by watching the (core) voltage on an oscilloscope
> > while modulating cpufreq/ACPI settings. The time used should be double
> > or triple the minimum for longterm stability. It would be better if
> > Mainboard manufacturers would specify this minimum time.
>
> That is suposed to be done via a BIOS table (with signature
> AMDK7PNOW!) for the powernow-k7 driver, but is used for the
> CPU only (I believe), and I guess that anyway this occur
> only when a valid core voltage is applied to the CPU (well,
> I hope).
> But perhaps this table do not give appropriate values on some system?
>
> Actually, I was wondering why the _PSS method (from ACPI) give
> a settling time of 125us, instead of 100us for some systems.

100us vs 125us won't matter unless the margin is too small already.

I don't know anything about the big CPU chip requirements as I have 
never read a datasheet  on on those big beasts.

My comments were related to the (analog side of the) power supply
limitations. 

IMHO mainboard Vcore switchers could do a step in 100us or so, or full scale 
over 10 steps or so, (weaker) main power supplies would likely have trouble 
as their switching frequency is much lower. Perhaps a mainboard designer
could comment?

Regards
Michael


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