From: Christoph Hellwig <hch@infradead.org>
To: linux-ia64@vger.kernel.org
Subject: Re: pgd_free, pmd_free, and pte_free trapping memory.
Date: Wed, 17 Mar 2004 16:53:01 +0000 [thread overview]
Message-ID: <20040317165301.A15751@infradead.org> (raw)
In-Reply-To: <20040316112424.GA20203@lnx-holt>
On Wed, Mar 17, 2004 at 10:20:16AM -0600, Jack Steiner wrote:
> The test harness ensures that the timing is done with warm TLBs & cold
> cache (data not in cpu caches):
>
> 3.1 usec 16K node local memory
> 6.1 usec 16K remote memory
>
> 12.5 usec 64K node local memory
> 24.5 usec 64K remote memory
>
> I ran this on Itanium 2 1300MHz cpus. However, processor core speed does
> not significantly affect timings since most time is spent waiting for
> off chip memory access.
Well, pages on the per-cpu list are supposed to be still cache hot..
next prev parent reply other threads:[~2004-03-17 16:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-03-16 11:24 pgd_free, pmd_free, and pte_free trapping memory Robin Holt
2004-03-16 14:48 ` Christoph Hellwig
2004-03-16 15:24 ` Robin Holt
2004-03-16 15:34 ` Christoph Hellwig
2004-03-17 12:27 ` Robin Holt
2004-03-17 16:20 ` Jack Steiner
2004-03-17 16:53 ` Christoph Hellwig [this message]
2004-03-17 17:10 ` David Mosberger
2004-03-17 20:33 ` Jack Steiner
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