Re: [RFC] Separate time support for using cpu timer

[Jun Sun <jsun@mvista.com>]

On Wed, Apr 21, 2004 at 03:19:45PM +0200, Maciej W. Rozycki wrote:
> On Tue, 20 Apr 2004, Jun Sun wrote:
> 
> > >  It makes it separate again -- more maintenance burden and a bigger
> > > opportunity to have functional divergence, sigh...
> > 
> > Pretty much true for lots of improvement we made in the past a couple of
> > years .... :)
> 
>  Hmm, s/improvement/hacks/, perhaps?
> 
> > >  Additionally I don't think using the CP0 Count & Compare registers for
> > > the system timer is the way to go.  It's rather a way to escape when
> > > there's no other possibility.  A lot of systems have a reliable external
> > > timer interrupt source and using it actually would free the CP0 registers
> > > for other uses, like profiling or a programmable interval timer.
> > 
> > I was rather neutral on this point until I started to add HRT/VST support to 
> > MIPS.  When adding such features you really just want one common timer code.
> > And the best choice for MIPS is cpu timer.
> 
>  Well, with the _hpt_ abstraction layer you have one common timer code,
> regardless of the actual timer hardware used.  If there's some
> functionality you miss there, we may discuss about possible solutions.
> 

Current high resolution timer code calls for two logic timers, one for
the old jiffy timer and one for intra-jiffy timer interrupt.

Even if you can extend hpt interface to accomondate this, each board
would still end up implementing a lot of complex code.

With cpu timer, however, we can "multiplex" the same timer to 
emulate both logical timers.  All boards using cpu timer can have HRT without 
any code change.

Jun