From: Ralf Baechle <ralf@linux-mips.org>
To: Guido Guenther <agx@sigxcpu.org>,
linux-mips@linux-mips.org, debian-toolchain@lists.debian.org
Subject: Re: TLS register
Date: Tue, 1 Jun 2004 14:15:20 +0200 [thread overview]
Message-ID: <20040601121520.GB25718@linux-mips.org> (raw)
In-Reply-To: <20040531230524.GB2785@bogon.ms20.nix>
On Mon, May 31, 2004 at 08:05:24PM -0300, Guido Guenther wrote:
> Hi,
> Now that gcc 3.4 has incompatible ABI changes (on o32 mostly affecting
> mipsel) I've been discussing with Thiemo if I'd be the right point to
> take this ABI change as a possibility to additionally reserve a TLS
> register.
> He suggested $24 (t8) another discussed possibility would be $27 (k1)
> which is already abused by the PS/2 folks for ll/sc emulation.
> Another possibility would be to reserve such a register only in the
> n32/n64 ABIs and let o32 stay without __thread and TLS forever.
Sigh, we'e been through this really often enough. Reserving a register
comes at a price so my approach was to implement a fast path in the
exception code. I've benchmarked that long time ago; it had less than
half the overhead than normal syscall and such a function would be subject
to normal code optimizations so calls should be few only. Alpha already
does something similar using their PAL code.
Ralf
next prev parent reply other threads:[~2004-06-01 12:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-05-31 23:05 TLS register Guido Guenther
2004-06-01 3:17 ` Steven J. Hill
2004-06-01 12:15 ` Ralf Baechle [this message]
2004-06-01 12:44 ` Kevin D. Kissell
2004-06-01 12:44 ` Kevin D. Kissell
2004-06-01 14:28 ` Maciej W. Rozycki
2004-06-01 19:21 ` David Daney
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