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Date: Mon, 2 Aug 2004 23:31:42 +0200
From: Ralf Baechle <ralf@linux-mips.org>
To: willem.acke@alcatel.be
Cc: linux-mips@linux-mips.org
Subject: Re: RM9000x2 TLB load exception
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On Mon, Aug 02, 2004 at 11:19:27AM +0200, willem.acke@alcatel.be wrote:

> I'm trying to port the mips-kernel to a RM9000x2 based custom board.
> The kernel file (mips 32) is loaded using VxWorks boot loader.
> I got the to the point where the kernel starts loading, but exits with a 
> 'TLB load exception'.
> After putting in a number of printks, it seems that it fails on 
> 'flush_icache_range' in arch/mips/mm/pg-r4k.c -> build_clear_page.
> Since I'm a newbie to this, any pointers to how to tackle this problem 
> would be appreciated.

Funny :-)  This is a particularly crazy function where I decieded to
generate the clear_function at runtime since we had to many versions
optimized for the one or other processor or configuration which had
become excessivly large.

> Exception:
> Tlb Load Exception
> Exception Program Counter: 0x00000000
> Status Register: 0x3404ff00
> Cause Register: 0x01100008
> Access Address : 0x00000000
> Task: 0x83e2c760 ""
[...]

The register dump is unseless since you didn't say what all the addresses
point to.

Other information that's needed to make sense out of a bug report would be:

 - gcc and binutils version used to compile the kernel
 - kernel version and also where did you get it from (linux-mips.org?)

  Ralf