Re: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.p

["Michael S. Zick" <mszick@goquest.com>]

On Fri August 13 2004 19:27, John David Anglin wrote:
> >   80:   d2 80 09 f4     shrpw r0,r20,16,r20
> >   84:   d2 80 39 f0     extrw,u,= r20,15,16,r0
> > 
> > Then checking chapter 7 on 'shrpw' it very clearly
> > states that this instruction effects only the right
> > half of the registers. (no mention of left half)
> 
> It actually says for 'shrpw' that the leftmost 32 bits of the target
> register (r20) are undefined.  If you had used a different target
> register, r20 would not have been affected.
> 
I need to learn to read better.

> 
> The documentation is a bit vague when it comes to condition tests
> when a result is discarded, but I believe that the test is done
> before the result is discarded.  It doesn't make any sense to test
> r0 which always reads as zero.
> 
Another vague thing -
Can you get a register stall (interlock) against gr0?
I.E:
op-code ....,destination Rx
op-code source Rx, .....
must wait for the store to Rx to be retired.
If Rx is GR0 - will the behavior be the same?
In tech. terms...
Is the discard prior to the retire stage of the
pipeline?
Is the discard even earlier than that in the pipeline? 
Does reference to GR0 count against the two 
register limit on issues?

I can find a partial answer - if the operation referencing
GR0 changes the flags - it seems that you can stall 
against the update of the flags in the PSW.
(or at least that would be reasonable to expect).

Mike
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