From: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
To: Arjan van de Ven <arjanv@redhat.com>
Cc: akpm@osdl.org, "Martin J. Bligh" <mbligh@aracnet.com>,
linux-mm@kvack.org
Subject: Re: [PATCH] shrink per_cpu_pages to fit 32byte cacheline
Date: Tue, 14 Sep 2004 07:01:52 -0300 [thread overview]
Message-ID: <20040914100152.GB23935@logos.cnet> (raw)
In-Reply-To: <20040914111329.GB21362@devserv.devel.redhat.com>
On Tue, Sep 14, 2004 at 01:13:29PM +0200, Arjan van de Ven wrote:
> On Tue, Sep 14, 2004 at 06:34:07AM -0300, Marcelo Tosatti wrote:
> > How come short access can cost 1 extra cycle? Because you need two "read bytes" ?
>
> on an x86, a word (2byte) access will cause a prefix byte to the
> instruction, that particular prefix byte will take an extra cycle during execution
> of the instruction and potentially reduces the parallal decodability of
> instructions....
OK thanks Arjan, where did you read this? The "Intel IA32 Optimization Guide" ?
Thanks for the info.
Andrew, we might want to revert the pagevec shrinkage part which changes couple
of variables to short - want to keep the "15" though.
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next prev parent reply other threads:[~2004-09-14 10:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-09-13 23:38 [PATCH] shrink per_cpu_pages to fit 32byte cacheline Marcelo Tosatti
2004-09-14 6:10 ` Arjan van de Ven
2004-09-14 9:34 ` Marcelo Tosatti
2004-09-14 11:13 ` Arjan van de Ven
2004-09-14 10:01 ` Marcelo Tosatti [this message]
2004-09-14 11:44 ` Arjan van de Ven
2004-09-14 22:45 ` Marcelo Tosatti
2004-09-15 0:57 ` Nick Piggin
2004-09-15 0:48 ` Marcelo Tosatti
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