From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Michael S. Zick" <mszick@wolfbutter.com>
Subject: Re: [parisc-linux] DIFF use 6-regs in copy_user_page_asm
Date: Tue, 4 Jan 2005 08:51:19 -0600
Message-ID: <200501040851.19806.mszick@wolfbutter.com>
References: <20050103061910.GJ15061@colo.lackof.org>
	<20050104061342.GE18497@tausq.org>
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On Tue January 4 2005 00:13, Randolph Chung wrote:
> > This patch adds one more cycle between the load and store of a
> > given register by using three pairs of registers instead of two.
> > I had previously quoted one of the PA-8xxx papers that indicated
> > L1 cache was 2 cycles latency.
> > With this diff, the unrolled part of the loop now meets that.
> > The prolog and epilogue obviously cannot.
> > 
> > If anyone can show me a workload that improves with this diff,
> > I'll apply it. Otherwise it's just an academic excercise.
> 
> i'd like to see numbers too, but i doubt you will see any. it appears
> that at least newer PA cpus do a sufficient amount of internal
> instruction reordering that you don't see a difference as long as there
> are enough pending instructions to keep the pipeline busy.
> 
One other possibility to keep in mind when testing: this is an
io sequence, no heavy register-register computations.

If the 4-regs + internal reordering has already saturated the
cpu-external busses...

Then even if the cpu-core can execute the 6-regs + internal
reordering more effectively, you will never see it outside
of the cpu.

You might have to borrow a buss analyzer from the hardware
lab to see if this is effecting your tests.

Mike
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