From: Jeremy Higdon <jeremy@sgi.com>
To: Ajit Prem <Ajit.Prem@motorola.com>
Cc: Jeff Garzik <jgarzik@pobox.com>, linux-ide@vger.kernel.org
Subject: Re: 31244 & sata_vsc & PPC
Date: Fri, 18 Feb 2005 22:01:49 -0800 [thread overview]
Message-ID: <20050219060149.GB720678@sgi.com> (raw)
In-Reply-To: <4213B24C.4030302@motorola.com>
On Wed, Feb 16, 2005 at 01:51:24PM -0700, Ajit Prem wrote:
>
> Thanks for the help.
>
> I printed the int_status register on interrupt
> entry into vsc_sata_interrupt and got 0x8300.
> According to the 31244 spec, this means (I have
> only 1 disk connected to port 1) :
>
> -- SATA Port 1 IDE Interrupt (0x8000)
> -- SATA Port 1 PHY Ready Interrupt (0x0200)
> -- SATA Port 1 Phy Change State Interrupt (0x0100)
>
> Any patch I can try?
>
> Thanks,
>
> AP
Interesting that I haven't seen this, but then I only have
the Vitesse part.
Jeff, I don't see where libata-core writes to the SCR_ERROR
register to clear the PHY Ready and Phy Change State interrupts.
Is this something that sata_vsc is supposed to do in its
interrupt handler? The core would miss such info if sata_vsc
did this . . . .
jeremy
next prev parent reply other threads:[~2005-02-19 6:03 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-02-16 19:05 31244 & sata_vsc & PPC Ajit Prem
2005-02-16 19:08 ` Jeff Garzik
2005-02-16 20:51 ` Ajit Prem
2005-02-19 6:01 ` Jeremy Higdon [this message]
2005-02-16 21:27 ` Ajit Prem
2005-02-16 22:25 ` Jeff Garzik
2005-02-17 1:21 ` Ajit Prem
2005-02-19 6:02 ` Jeremy Higdon
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