From: "David S. Miller" <davem@davemloft.net>
To: sparclinux@vger.kernel.org
Subject: Re: SMP on virtually indexed/tagged cache
Date: Wed, 13 Apr 2005 19:29:53 +0000 [thread overview]
Message-ID: <20050413122953.4e15eb13.davem@davemloft.net> (raw)
In-Reply-To: <737167738@web.de>
On Wed, 13 Apr 2005 11:26:33 +0200
"Konrad Eisele" <eiselekd@web.de> wrote:
> "David S. Miller" <davem@davemloft.net> schrieb am 12.04.05 21:28:47:
> >
> > On Tue, 12 Apr 2005 14:50:54 +0200
> > "Konrad Eisele" <eiselekd@web.de> wrote:
> >
> > > I trying to get sparc32-smp run on a Leon3 sparc,
> > > it uses a virtually indexed/tagged cache. Is it possible
> > > to run smp on such a processor?
> >
> > Yes, it's just painful. Model your cache flushing on the
> > sun4c code.
> > -
>
> It's difficult to understand how smp works when cache coherency isn't
> done by hardware.
Oh nevermind, yes that is next to impossible. If the cpus aren't
doing any cache coherency protocol on the system bus, you're basically
out of luck.
I forgot that physical indexing was necessary for a cache coherency
protocol since the system bus works with physical addresses.
prev parent reply other threads:[~2005-04-13 19:29 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-04-12 12:50 SMP on virtually indexed/tagged cache Konrad Eisele
2005-04-12 19:19 ` David S. Miller
2005-04-13 9:26 ` Konrad Eisele
2005-04-13 19:29 ` David S. Miller [this message]
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