From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1DNG4b-0000rK-TV for qemu-devel@nongnu.org; Sun, 17 Apr 2005 16:08:53 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1DNG2x-0000YX-1Q for qemu-devel@nongnu.org; Sun, 17 Apr 2005 16:07:16 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DNG2m-0000Nw-7r for qemu-devel@nongnu.org; Sun, 17 Apr 2005 16:07:00 -0400 Received: from [65.74.133.9] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtp (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.34) id 1DNFoV-0004ge-1S for qemu-devel@nongnu.org; Sun, 17 Apr 2005 15:52:15 -0400 From: Paul Brook Date: Sun, 17 Apr 2005 20:50:47 +0100 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200504172050.47959.paul@codesourcery.com> Subject: [Qemu-devel] [patch] Fix dumping of arm registers Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The patch below fixes a thinko in the arm cpu state dumping so the FPSCR is only displayed once. Paul Index: target-arm/translate.c =================================================================== RCS file: /cvsroot/qemu/qemu/target-arm/translate.c,v retrieving revision 1.20 diff -u -p -r1.20 translate.c --- target-arm/translate.c 17 Apr 2005 19:16:13 -0000 1.20 +++ target-arm/translate.c 17 Apr 2005 19:46:34 -0000 @@ -2153,8 +2153,8 @@ void cpu_dump_state(CPUState *env, FILE i * 2 + 1, (int)s0.i, s0.s, i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower, d.d); - cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.fpscr); } + cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.fpscr); } target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)