From: Dave Jones <davej@redhat.com>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [RFC] Cachemap for 2.6.12rc4-mm1. Was Re: [PATCH] enhance x86 MTRR handling
Date: Fri, 13 May 2005 19:42:11 -0400 [thread overview]
Message-ID: <20050513234211.GF13846@redhat.com> (raw)
In-Reply-To: <428539EA.7000406@zytor.com>
On Fri, May 13, 2005 at 04:36:10PM -0700, H. Peter Anvin wrote:
> The Efficeon (TM8xxx) series does have PAT.
1:1 with the Intel implementation I assume based on your earlier comments?
> > > >+ * Note: On Athlon cpus PAT2/PAT3 & PAT6/PAT7 are both Uncacheable
> > since > >+ * there is no uncached type.
> > > If one sets the PAT to "uncached", does one get the same function as
> > > "uncachable"?
> >
> >AIUI, only as long as we don't have an MTRR covering the same range marked
> >WC.
> >It seems to be the only thing I could find documenting the differences
> >between 'uncached' and 'uncacheable' in this context.
> >Though I've only looked through the Intel & AMD K8 docs, I don't have
> >the K7 ones to hand.
> >
>
> I mean, on the Athlon series, is it really necessary to use a different
> value?
I'd have to dig out the docs and check.
Dave
next prev parent reply other threads:[~2005-05-13 23:43 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-05-12 9:08 [PATCH] enhance x86 MTRR handling Jan Beulich
2005-05-12 16:18 ` Dave Jones
2005-05-12 17:02 ` David Addison
2005-05-12 21:41 ` [RFC] Cachemap for 2.6.12rc4-mm1. Was " Dave Jones
2005-05-13 13:29 ` Andi Kleen
2005-05-13 14:24 ` Dave Hansen
2005-05-13 14:35 ` Andi Kleen
2005-05-13 15:52 ` Dave Jones
2005-05-18 22:01 ` Terence Ripperda
2005-05-18 22:03 ` Andi Kleen
2005-05-18 22:15 ` Terence Ripperda
2005-05-18 22:42 ` Andi Kleen
2005-05-19 3:57 ` Randy Dunlap
2005-05-13 22:40 ` H. Peter Anvin
2005-05-13 23:23 ` Dave Jones
2005-05-13 23:36 ` H. Peter Anvin
2005-05-13 23:42 ` Dave Jones [this message]
2005-05-13 23:49 ` H. Peter Anvin
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