From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1E4as6-0000K7-6C for qemu-devel@nongnu.org; Mon, 15 Aug 2005 05:03:06 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1E4as2-0000Hx-J2 for qemu-devel@nongnu.org; Mon, 15 Aug 2005 05:03:04 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1E4as1-00009F-0k for qemu-devel@nongnu.org; Mon, 15 Aug 2005 05:03:01 -0400 Received: from [62.254.210.129] (helo=bacchus.net.dhis.org) by monty-python.gnu.org with esmtp (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.34) id 1E4axg-0006pN-0m for qemu-devel@nongnu.org; Mon, 15 Aug 2005 05:08:52 -0400 Date: Mon, 15 Aug 2005 09:52:10 +0100 From: Ralf Baechle Message-ID: <20050815085210.GA7390@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH 1/3] Fix MIPS counter / compare interrupt Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabrice Bellard , qemu-devel@nongnu.org The count / compare interrupt is wired to the CPU's internal interrupt controller, not a PIC. hw/mips_r4k.c | 10 ++++++++-- target-mips/helper.c | 12 +++++++++++- 2 files changed, 19 insertions(+), 3 deletions(-) Index: qemu-mips/hw/mips_r4k.c =================================================================== --- qemu-mips.orig/hw/mips_r4k.c +++ qemu-mips/hw/mips_r4k.c @@ -72,7 +75,8 @@ void cpu_mips_store_count (CPUState *env void cpu_mips_store_compare (CPUState *env, uint32_t value) { cpu_mips_update_count(env, cpu_mips_get_count(env), value); - pic_set_irq(5, 0); + cpu_single_env->CP0_Cause &= ~0x00008000; + cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); } static void mips_timer_cb (void *opaque) @@ -86,7 +90,8 @@ static void mips_timer_cb (void *opaque) } #endif cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); - pic_set_irq(5, 1); + cpu_single_env->CP0_Cause |= 0x00008000; + cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); } void cpu_mips_clock_init (CPUState *env)