From: Matthew Wilcox <matthew@wil.cx>
To: Nick Piggin <nickpiggin@yahoo.com.au>
Cc: "David S. Miller" <davem@davemloft.net>, linux-arch@vger.kernel.org
Subject: Re: [Fwd: [PATCH 2.6.13] lockless pagecache 2/7]
Date: Sun, 4 Sep 2005 07:28:52 -0600 [thread overview]
Message-ID: <20050904132852.GA4316@parisc-linux.org> (raw)
In-Reply-To: <431807DD.5030105@yahoo.com.au>
On Fri, Sep 02, 2005 at 06:05:49PM +1000, Nick Piggin wrote:
> David S. Miller wrote:
> >Sparc32 lacks compare and exchange. I think PARISC lacks it
> >as well.
> >
> >For these older SMP systems, at best you can assume there
> >is some kind of spinlock and perhaps a straight atomic
> >exchange instruction. You really can't assume the existance
> >of compare-and-swap.
> >
>
> Thanks David, I suspected as much.
>
> PARISC emulates cmpxchg. I suspect sparc could do the same?
> (provided all access goes through the atomic_xxx accessors)
If Sparc has atomic stores to aligned addresses (and I bet it does),
then the PA-RISC style emulation should work just fine.
prev parent reply other threads:[~2005-09-04 13:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-09-02 6:36 [Fwd: [PATCH 2.6.13] lockless pagecache 2/7] Nick Piggin
2005-09-02 7:39 ` David S. Miller
2005-09-02 8:05 ` Nick Piggin
2005-09-04 13:28 ` Matthew Wilcox [this message]
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