Re: xen 3.0 for AMD Pacifica

[Dave Feustel <dfeustel@verizon.net>]

On Tuesday 25 October 2005 09:53, Anthony Liguori wrote:
> Dave Feustel wrote:
> 
> >>We intend to add support for x86 h/w virtualization extensions 
> >>as information about them becomes available.
> >>    
> >>
> >
> >What information is needed beyond the Pacifica documentation already
> >provided by AMD and the Vanderpool docs provided by Intel?
> >  
> >
> I don't know where you're quoting from, but both specs are out publicly.

I know. I have both. What I was asking is whether the info in those documents
is sufficient to make Xen work with  the hardware of both chips, or is additional 
info needed (and still not available)?
 
> As Mark mentions, there's quite a bit of work to go from specs to 
> implementation though.
> 
> Both VT and Pacifica are pretty similiar in the basic idea that they 
> allow the processor to be put in a mode where 30 or so events that 
> normally don't trap actually do trap.

Pacifica has a new paging mode (paged real mode) made possible by the 
Opteron on-chip memory controller. This feature is not present in VT.

> Just having the processor trap though doesn't get you virtualization 
> :-)  Each of those events has to be handled, and often emulated.  Throw 
> in shadow paging and IO emulation and it's all rather complicated.
> 
> Plus, there's not much that can be done without having the hardware at 
> this point.
> 
> >Is there any possibility of setting up a mailing list directed specifically at
> >xen 3.0 hardware supported virtualization?
> >  
> >
> There are an awful lot of Xen mailing lists at this point.  What would 
> be *really* useful is having some content on the wiki that went into 
> more depth about VT/Pacifica.
> 
> Regards,
> 
> Anthony Liguori
> 
> >Thanks,
> >Dave Feustel
> >
> >
> >  
> >
> 
> 
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