From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1EcR9K-0007KJ-3x for qemu-devel@nongnu.org; Wed, 16 Nov 2005 12:32:46 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1EcR9H-0007Hf-G3 for qemu-devel@nongnu.org; Wed, 16 Nov 2005 12:32:45 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1EcR9H-0007HO-7Y for qemu-devel@nongnu.org; Wed, 16 Nov 2005 12:32:43 -0500 Received: from [206.46.252.40] (helo=vms040pub.verizon.net) by monty-python.gnu.org with esmtp (Exim 4.34) id 1EcR9G-0008G2-CP for qemu-devel@nongnu.org; Wed, 16 Nov 2005 12:32:42 -0500 Received: from [71.97.178.169] by vms040.mailsrvcs.net (Sun Java System Messaging Server 6.2-4.02 (built Sep 9 2005)) with ESMTPA id <0IQ200DUF62E8OJ8@vms040.mailsrvcs.net> for qemu-devel@nongnu.org; Wed, 16 Nov 2005 11:32:39 -0600 (CST) Date: Wed, 16 Nov 2005 12:32:37 -0500 From: Dave Feustel Subject: Re: [Qemu-devel] Cell processor In-reply-to: <200511161642.20960.paul@codesourcery.com> Message-id: <200511161232.37855.dfeustel@verizon.net> MIME-version: 1.0 Content-type: text/plain; charset=iso-8859-1 Content-transfer-encoding: 7bit Content-disposition: inline References: <200511160730.24425.dfeustel@verizon.net> <4ad99e050511160510w64e15f3bpd7391eb670b31c32@mail.gmail.com> <200511161642.20960.paul@codesourcery.com> Reply-To: dfeustel@mindspring.com, qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: qemu-devel@nongnu.org On Wednesday 16 November 2005 11:42, Paul Brook wrote: > On Wednesday 16 November 2005 13:10, Lars Roland wrote: > > On 11/16/05, Dave Feustel wrote: > > > Is there any chance that simulation of the > > > IBM Cell processor will be added to Qemu? > > > > Although this would be great, I am not sure how easy it is to get a > > accurate simulation of this chip. The cell architecture consists of > > both a power processor element (PPE) and 8 synergistic processor > > elements (SPEs) while the PPE is a conventional microprocessor the > > SPEs are far from so > > > > The point of the cell is to get the PPE to prepare tasks that can be > > executed in a parallel distributed manner across all the SPEs and I am > > afraid that this scheduling is going to be very hard to implement > > correctly - I may however be proven wrong. > > It depends how accurate you want the simulation to be. A cycle accurate > simulator is probably going to be trickier. If you don't need cycle accuracy > it shouldn't be worse than any other multiprocessor system. > > The only real fundamental missing feature in QEMU is SMP guest support. > The main PPE is a virtual 2-way 64-bit PowerPC core. Qemu ppc64 is currently > incomplete, but that's fixable. > > I'd expect the SPE to be very easy to emulate. These are simple RISC vector > cores with their own local memory, no MMU, and a DMA/mailbox engine to > communicate with the rest of the system. > > It's a significant amount of work, but other than the SMP issue (which needs > fixing for other targets anyway) it's not excessively hard. Slightly off topic, but AMD has just announced its intention to ship a 4-core Opteron chip in 2007. The 4-core chip will use AMD's upcoming m2 socket. > Paul > -- Switch to Secure OpenBSD with a KDE desktop!!! NOW with Virtual PC OS support via QEMU and Beowulf clustering using PETSc and MPICH2!