From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1EcRig-0002VD-Tw for qemu-devel@nongnu.org; Wed, 16 Nov 2005 13:09:19 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1EcRic-0002Sw-Vp for qemu-devel@nongnu.org; Wed, 16 Nov 2005 13:09:18 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1EcRic-0002Sd-CR for qemu-devel@nongnu.org; Wed, 16 Nov 2005 13:09:14 -0500 Received: from [65.74.133.11] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtp (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.34) id 1EcRia-0002IS-NP for qemu-devel@nongnu.org; Wed, 16 Nov 2005 13:09:13 -0500 From: Paul Brook Subject: Re: [Qemu-devel] Cell processor Date: Wed, 16 Nov 2005 18:08:58 +0000 References: <200511160730.24425.dfeustel@verizon.net> <200511161232.37855.dfeustel@verizon.net> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200511161808.59491.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org > > Slightly off topic, but AMD has just announced its intention to ship a > > 4-core Opteron chip in 2007. The 4-core chip will use AMD's upcoming m2 > > socket. > > isn't writing a OS for dual (or n) core chips hell ? It's no different to any other SMP system, and most serious OS have been doing that for years. You might want to use slightly different load balancing heuristics for big machines, but most big multiprocessor systems are already NUMA anyway so that's nothing new. Paul