Re: MIPS - 64bit woes

[Ralf Baechle <ralf@linux-mips.org>]

On Thu, Nov 17, 2005 at 05:21:27PM -0800, Jim Gifford wrote:

> Got a fix for 2.6.14, http://ftp.jg555.com/cobalt/fix-2.6.14.
> 
> Ralf, I know this is probably not the fix you would like to see, any 
> suggestions.
> 
> diff -Naur linux-mips-2.6.14.orig/arch/mips/kernel/cpu-probe.c 
> linux-mips-2.6.14/arch/mips/kernel/cpu-probe.c
> --- linux-mips-2.6.14.orig/arch/mips/kernel/cpu-probe.c    2005-11-17 
> 11:42:19.000000000 -0800
> +++ linux-mips-2.6.14/arch/mips/kernel/cpu-probe.c    2005-11-17 
> 15:00:11.000000000 -0800
> @@ -121,7 +105,6 @@
>     case CPU_24K:
>     case CPU_25KF:
>     case CPU_34K:
> -     case CPU_PR4450:
>         cpu_wait = r4k_wait;
>         printk(" available.\n");
>         break;

Ehhh?

As for the remainder of your patch - the fact that this actually works
made me notice that there is no cpu-features-override.h for Cobalt which
means that Cobalt kernels carry a rather heavyweight generic cachecode
including spinlocks and all sorts of atomic operations that will at
runtime select between ll/sc and non-ll/sc variants.  That's slow and
I would rather suggest you get rid of that overhead by simply
pretending not to have ll/sc at all on Cobalt but putting something like

#ifdef CONFIG_64BIT
#define cpu_has_llsc            0
#else
#define cpu_has_llsc            1
#endif

into the Cobalt cpu-features-override.h.

  Ralf