Re: [discuss] [patch] x86_64: align and pad x86_64 GDT on page boundary

[Ravikiran G Thirumalai <kiran@scalex86.org>]

On Fri, Dec 09, 2005 at 11:59:21PM +0100, Andi Kleen wrote:
> On Fri, Dec 09, 2005 at 03:01:27PM -0800, Rohit Seth wrote:
> > > > For the BP case it's ok as 
> > > > long as the beginning is correctly aligned and the rest 
> > > > is read-only.
> > > 
> > > Just that any writes on the bp GDT will invalidate the idt_table cacheline,
> > > which is read mostly (as Nippun pointed out).  So could we keep the padding
> > > as it is for the BP too? 
> > > 
> > 
> > Do you write into GDT often for this to be an issue.  The reason I'm
> 
> The context switch writes into the GDT to switch around the TLS segments

Yup.

> 
> > asking this because the per-cpu IDTs that Andi refered in the future.
> > If we are really not using too many bytes in GDT then rest of the page
> > can be used for IDT and such mostly RO data.
> 
> Once I implement that it can be shared with that page.

Yes, that will be nice.

Thanks,
Kiran