From: Ralf Baechle <ralf@linux-mips.org>
To: Martin Michlmayr <tbm@cyrius.com>
Cc: linux-mips@linux-mips.org
Subject: Re: Fix a CPU definition for Cobalt
Date: Fri, 20 Jan 2006 16:19:58 +0100 [thread overview]
Message-ID: <20060120151958.GC30415@linux-mips.org> (raw)
In-Reply-To: <20060120151005.GH4343@deprecation.cyrius.com>
On Fri, Jan 20, 2006 at 03:10:05PM +0000, Martin Michlmayr wrote:
> * Ralf Baechle <ralf@linux-mips.org> [2006-01-20 16:01]:
> > > > pointer is eventually called as a function. So I suggest this below.
> > > > Can you test it?
> > > Doesn't work.
> > Indeed - for quite obvioius reasons even. I hope I now covered all cases
> > in the new patch below.
>
> You attached the SERIO patch. ;-)
Just checking your attention ;-)
Ralf
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 422b55f..614dceb 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -235,7 +235,9 @@ static inline void r4k_blast_scache_page
{
unsigned long sc_lsize = cpu_scache_line_size();
- if (sc_lsize == 16)
+ if (scache_size == 0)
+ r4k_blast_scache_page = no_sc_noop;
+ else if (sc_lsize == 16)
r4k_blast_scache_page = blast_scache16_page;
else if (sc_lsize == 32)
r4k_blast_scache_page = blast_scache32_page;
@@ -251,7 +253,9 @@ static inline void r4k_blast_scache_page
{
unsigned long sc_lsize = cpu_scache_line_size();
- if (sc_lsize == 16)
+ if (scache_size == 0)
+ r4k_blast_scache_page = no_sc_noop;
+ else if (sc_lsize == 16)
r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
else if (sc_lsize == 32)
r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
@@ -495,7 +499,7 @@ static inline void local_r4k_flush_icach
}
}
- if (!cpu_icache_snoops_remote_store) {
+ if (!cpu_icache_snoops_remote_store && scache_size) {
if (end - start > scache_size) {
r4k_blast_scache();
} else {
@@ -728,7 +732,7 @@ static void local_r4k_flush_cache_sigtra
R4600_HIT_CACHEOP_WAR_IMPL;
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
- if (!cpu_icache_snoops_remote_store)
+ if (!cpu_icache_snoops_remote_store && scache_size)
protected_writeback_scache_line(addr & ~(sc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
if (MIPS4K_ICACHE_REFILL_WAR) {
next prev parent reply other threads:[~2006-01-20 15:17 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-01-19 19:24 Fix a CPU definition for Cobalt Martin Michlmayr
2006-01-19 21:04 ` Ralf Baechle
2006-01-19 21:45 ` Martin Michlmayr
2006-01-20 15:01 ` Ralf Baechle
2006-01-20 15:10 ` Martin Michlmayr
2006-01-20 15:19 ` Ralf Baechle [this message]
2006-01-20 16:00 ` Martin Michlmayr
2006-02-17 19:14 ` Martin Michlmayr
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