From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Mason Subject: Re: Custom Hardware Acceleration Date: Thu, 26 Jan 2006 14:48:03 -0600 Message-ID: <20060126204802.GF17021@us.ibm.com> References: <43D88DCD.4050006@stanford.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <43D88DCD.4050006@stanford.edu> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Jad Naous Cc: xen-devel@lists.xensource.com List-Id: xen-devel@lists.xenproject.org On Thu, Jan 26, 2006 at 12:52:29AM -0800, Jad Naous wrote: > Hi all, > I am exploring the possibility of designing a custom hardware > acceleration solution using an ASIC or an FPGA to accelerate some part > of Xen. Basically, I am looking for some part of the code that could be > built in hardware to make it faster. Does anybody know where I could get > some statistics on the code, such as the most called functions, the most > parallelizable functions, etc... If you could think of something that > would be useful in HW I would be very interested to know. > Thanks, > Jad. You could make a custom NIC FPGA that can handle paravirtulized network receive. The NIC can inspect the destination MAC address of the incomming packet, and DMA it to a pre-alloced space in the domU (removing the need for the page flip). It will require modifing the xen network drivers, but should be pretty cool. Thanks, Jon