From: Jack Steiner <steiner@sgi.com>
To: linux-ia64@vger.kernel.org
Subject: Re: PMU and timer interrupts
Date: Thu, 09 Feb 2006 19:10:22 +0000 [thread overview]
Message-ID: <20060209191022.GA4761@sgi.com> (raw)
In-Reply-To: <20060209171648.GA26865@frankl.hpl.hp.com>
On Thu, Feb 09, 2006 at 10:39:49AM -0800, Stephane Eranian wrote:
> Tony, Jack,
>
> On Thu, Feb 09, 2006 at 10:20:18AM -0800, Luck, Tony wrote:
> > >It was recently pointed out to me that the PMU interrupt
> > >vector is set to 0xee just below the timer interrupt at 0xef.
> > >As such, the timer interrupt has higher priority than the PMU
> > >interrupt. This would make sense except that a side effect is
> > >that it is not possible to collect samples from within the timer
> > >interrupt, i.e. we have a blind spot. Another side effect is
> > >that events happening during the timer handler, may be falsely
> > >attributed to the point where we write the EOI register.
> > >
> > >I looked at the timer_interrupt() path, and I did not see anything special
> > >that would prevent us from swapping the interrupt vectors thereby removing
> > >the blind spot we have.
> > >
> > >Does anybody see a problem with this?
> >
> > How much would this help? Both 0xEF and 0xEE are part of the
> > same priority class (see table 5-8 on p. 2-112 of SDM).
> >
> Correct me if I am wrong, but the class masking happens only with TPR
> masking. So if we had timer=0xee, PMU=0xef and if the kernel does not
> raise the TPR class masking to the priority class of 0xef/0xee, then
> we could still get a PMU interrupt while executing the timer handler.
>
What you say is true. However, the kernel does use the TPR to enforce
priority classes:
void
ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
{
...
saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
while (vector != IA64_SPURIOUS_INT_VECTOR) {
if (!IS_RESCHEDULE(vector)) {
ia64_setreg(_IA64_REG_CR_TPR, vector);
__do_IRQ(local_vector_to_irq(vector), regs);
....
}
Use of priority classes prevents excessive recursion. Without it, as a worse case,
- a priority 16 interrupt could be interrupted by a priority 17
- which is interrupted by an 18
- which is interrupted by an 19
- which is interrupted by an 20
- etc. and the kernel stack goes BOOM :-)
Priority classes limits the recursion to 15 levels at most.
next prev parent reply other threads:[~2006-02-09 19:10 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-02-09 17:16 PMU and timer interrupts Stephane Eranian
2006-02-09 18:16 ` Jack Steiner
2006-02-09 18:20 ` Luck, Tony
2006-02-09 18:39 ` Stephane Eranian
2006-02-09 19:10 ` Jack Steiner [this message]
2006-02-09 19:11 ` Stephane Eranian
2006-02-10 13:35 ` Stephane Eranian
2006-02-10 13:54 ` Jes Sorensen
2006-02-10 20:33 ` Chen, Kenneth W
2006-02-10 21:22 ` Stephane Eranian
2006-02-10 23:04 ` Chen, Kenneth W
2006-02-10 23:21 ` Stephane Eranian
2006-02-10 23:26 ` Jes Sorensen
2006-02-13 10:38 ` Stephane Eranian
2006-02-13 10:53 ` Jes Sorensen
2006-02-13 20:01 ` Stephane Eranian
2006-02-13 20:12 ` Stephane Eranian
2006-02-13 20:13 ` Chen, Kenneth W
2006-02-13 20:32 ` Chen, Kenneth W
2006-02-13 21:26 ` Keith Owens
2006-02-13 22:49 ` Chen, Kenneth W
2006-02-13 23:46 ` Stephane Eranian
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