From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1FABge-0008HZ-On for qemu-devel@nongnu.org; Fri, 17 Feb 2006 14:54:41 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1FAAt5-0006iV-8h for qemu-devel@nongnu.org; Fri, 17 Feb 2006 14:03:39 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1FA8qf-0002ut-35 for qemu-devel@nongnu.org; Fri, 17 Feb 2006 11:52:49 -0500 Received: from [193.7.176.20] (helo=bender.bawue.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.52) id 1FA8w3-0003jX-4v for qemu-devel@nongnu.org; Fri, 17 Feb 2006 11:58:23 -0500 Received: from lagash (unknown [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 6E6C245695 for ; Fri, 17 Feb 2006 17:52:46 +0100 (MET) Received: from ths by lagash with local (Exim 4.60) (envelope-from ) id 1FA8qw-0000bL-9b for qemu-devel@nongnu.org; Fri, 17 Feb 2006 16:53:06 +0000 Date: Fri, 17 Feb 2006 16:53:06 +0000 Subject: Re: [Qemu-devel] [PATCH] Trivial code improvement Message-ID: <20060217165306.GG23684@networkno.de> References: <20060216163204.GB23684@networkno.de> <20060216222747.GA1652@nevyn.them.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20060216222747.GA1652@nevyn.them.org> From: Thiemo Seufer Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Thu, Feb 16, 2006 at 05:27:47PM -0500, Daniel Jacobowitz wrote: > On Thu, Feb 16, 2006 at 04:32:04PM +0000, Thiemo Seufer wrote: > > Index: cpu-exec.c > > =================================================================== > > RCS file: /sources/qemu/qemu/cpu-exec.c,v > > retrieving revision 1.73 > > diff -u -p -r1.73 cpu-exec.c > > --- cpu-exec.c 8 Feb 2006 22:43:39 -0000 1.73 > > +++ cpu-exec.c 16 Feb 2006 15:21:03 -0000 > > @@ -549,7 +549,7 @@ int cpu_exec(CPUState *env1) > > do_interrupt(env); > > } > > #endif > > - if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { > > + if (interrupt_request & CPU_INTERRUPT_EXITTB) { > > env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; > > /* ensure that no TB jump will be modified as > > the program flow was changed */ > > Didn't we go round this recently? do_interrupt might modify > env->interrupt_request - see target-arm/helper.c for instance. Hm, interesting side-effect. Updated patch appended. Thiemo Index: cpu-exec.c =================================================================== RCS file: /sources/qemu/qemu/cpu-exec.c,v retrieving revision 1.73 diff -u -p -r1.73 cpu-exec.c --- cpu-exec.c 8 Feb 2006 22:43:39 -0000 1.73 +++ cpu-exec.c 17 Feb 2006 16:45:38 -0000 @@ -549,6 +549,8 @@ int cpu_exec(CPUState *env1) do_interrupt(env); } #endif + /* Don't use the cached interupt_request value, + do_interrupt may have updated the EXITTB flag. */ if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as Index: target-mips/helper.c =================================================================== RCS file: /sources/qemu/qemu/target-mips/helper.c,v retrieving revision 1.8 diff -u -p -r1.8 helper.c --- target-mips/helper.c 5 Dec 2005 19:59:36 -0000 1.8 +++ target-mips/helper.c 17 Feb 2006 16:45:39 -0000 @@ -220,7 +219,6 @@ int cpu_mips_handle_mmu_fault (CPUState exception = EXCP_TLBS; else exception = EXCP_TLBL; - error_code = 0; break; case -4: /* TLB match but 'D' bit is cleared */ @@ -350,7 +349,6 @@ void do_interrupt (CPUState *env) cause = 4; goto set_EPC; case EXCP_TLBL: - case EXCP_TLBF: cause = 2; if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL)) offset = 0x000;