From: "Michael S. Zick" <mszick@morethan.org>
To: parisc-linux@lists.parisc-linux.org
Cc: Kyle McMartin <kyle@mcmartin.ca>,
John David Anglin <dave@hiauly1.hia.nrc.ca>
Subject: Re: [parisc-linux] Heavy Iron Reference Docs
Date: Sun, 30 Apr 2006 18:28:26 -0500 [thread overview]
Message-ID: <200604301828.26318.mszick@morethan.org> (raw)
In-Reply-To: <200604301801.23210.mszick@morethan.org>
On Sun April 30 2006 18:01, Michael S. Zick wrote:
>
> Scratches head...
>
> I wonder where Joel has his processors installed in relation to the
> two busses? Both on same buss or one per buss? Would his lockups
> go away if he picked the other relationship?
>
> I will ask him. (or perhaps I just did)
>
Browsing old parisc spinlock code, I find a comment that the N4K
can only have one outstanding PxTLB transaction at a time.
Is it not the PxTLB transactions that implement the inter-processor
coherency?
Which is of course required for inter-processor spinlocks to work.
And, of course, this being Linux, the queue is protected by a spinlock!
Did someone just shoot themselves in the foot?
Mike
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next prev parent reply other threads:[~2006-04-30 23:28 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-04-30 3:50 [parisc-linux] Heavy Iron Reference Docs Michael S. Zick
2006-04-30 4:36 ` John David Anglin
2006-04-30 17:13 ` Kyle McMartin
2006-04-30 21:25 ` John David Anglin
2006-04-30 23:01 ` Michael S. Zick
2006-04-30 23:28 ` Michael S. Zick [this message]
2006-05-02 6:24 ` Grant Grundler
2006-05-02 11:27 ` Michael S. Zick
2006-04-30 23:30 ` John David Anglin
2006-05-01 3:23 ` Michael S. Zick
2006-05-02 6:00 ` Grant Grundler
2006-05-02 15:10 ` John David Anglin
2006-05-02 15:13 ` Kyle McMartin
2006-05-02 15:41 ` John David Anglin
2006-04-30 7:03 ` Grant Grundler
2006-04-30 13:12 ` Michael S. Zick
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