From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Fb4JV-0004mc-BO for qemu-devel@nongnu.org; Tue, 02 May 2006 19:29:53 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Fb4JS-0004hy-6n for qemu-devel@nongnu.org; Tue, 02 May 2006 19:29:51 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Fb4JR-0004hh-R3 for qemu-devel@nongnu.org; Tue, 02 May 2006 19:29:49 -0400 Received: from [193.7.176.20] (helo=bender.bawue.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.52) id 1Fb4Jh-0003K0-ED for qemu-devel@nongnu.org; Tue, 02 May 2006 19:30:05 -0400 Received: from lagash (88-106-136-76.dynamic.dsl.as9105.com [88.106.136.76]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 89F3044694 for ; Wed, 3 May 2006 01:29:46 +0200 (MEST) Received: from ths by lagash with local (Exim 4.61) (envelope-from ) id 1Fb4J2-0003XP-D0 for qemu-devel@nongnu.org; Wed, 03 May 2006 00:29:24 +0100 Date: Wed, 3 May 2006 00:29:24 +0100 Subject: Re: [Qemu-devel] qemu/hw mips_r4k.c Message-ID: <20060502232924.GJ5004@networkno.de> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: From: Thiemo Seufer Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Fabrice Bellard wrote: > CVSROOT: /sources/qemu > Module name: qemu > Branch: > Changes by: Fabrice Bellard 06/05/02 22:18:28 > > Modified files: > hw : mips_r4k.c > > Log message: > performance boost (on P4 hosts at least, rdtsc is a _very_ bad random generator) > > CVSWeb URLs: > http://cvs.savannah.gnu.org/viewcvs/qemu/qemu/hw/mips_r4k.c.diff?tr1=1.15&tr2=1.16&r1=text&r2=text Does this really provide a measurable performance improvement? Real hardware simply increments cp0_random together with the cycle counter, this is randomized enough for TLB entry replacement. Thiemo