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Date: Mon, 15 May 2006 02:19:01 +0100
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From: Thiemo Seufer <ths@networkno.de>
Subject: [Qemu-devel] [PATCH 2/8] Mips improvements
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To: qemu-devel@nongnu.org

Hello All,

this patch enables disassembly of all instructions the mips
disassembler knows about.


Thiemo


Index: qemu-work/mips-dis.c
===================================================================
--- qemu-work.orig/mips-dis.c	2006-05-15 01:13:13.000000000 +0100
+++ qemu-work/mips-dis.c	2006-05-15 01:20:23.000000000 +0100
@@ -528,6 +528,7 @@
    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
    test, or zero if no CPU specific ISA test is desired.  */
 
+#if 0
 #define OPCODE_IS_MEMBER(insn, isa, cpu)				\
     (((insn)->membership & isa) != 0					\
      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)	\
@@ -543,6 +544,10 @@
      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)	\
      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)	\
      || 0)	/* Please keep this term for easier source merging.  */
+#else
+#define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
+    (1 != 0)
+#endif
 
 /* This is a list of macro expanded instructions.