From: Ralf Baechle <ralf@linux-mips.org>
To: "Maciej W. Rozycki" <macro@linux-mips.org>
Cc: art <art@sigrand.ru>, linux-mips@linux-mips.org
Subject: Re: Problem with TLB mcheck!
Date: Wed, 24 May 2006 16:52:07 +0100 [thread overview]
Message-ID: <20060524155207.GB25452@linux-mips.org> (raw)
In-Reply-To: <Pine.LNX.4.64N.0605241605120.7887@blysk.ds.pg.gda.pl>
On Wed, May 24, 2006 at 04:11:12PM +0100, Maciej W. Rozycki wrote:
> > Depends on when exactly a CPU will raise the machine check. On some cores
> > the information in registers is totally useless if not even missloading.
>
> We have got PRId to filter out these. Though rev. 2 of the architecture
> limits conditions when to raise the exception so it may eventually be a
> non-issue.
Doesn't really help, the exception is asynchronous by definition, so the
CPU can be far away by the time it's struck be the lightning bolt.
Machine check is just a _bad_ place to be.
> > But generally a good idea, patch below.
>
> Except Index would be a bit more useful than HI. ;-)
Index may not matter at all in case of a TLBWR. But yes, will include
index in the patch.
Ralf
next prev parent reply other threads:[~2006-05-24 15:52 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-05-24 9:35 Problem with TLB mcheck! art
2006-05-24 12:45 ` Maciej W. Rozycki
2006-05-24 14:49 ` Ralf Baechle
2006-05-24 15:11 ` Maciej W. Rozycki
2006-05-24 15:52 ` Ralf Baechle [this message]
2006-05-24 16:29 ` Maciej W. Rozycki
2006-05-26 11:40 ` Re[2]: " art
-- strict thread matches above, loose matches on Subject: below --
2006-05-31 3:42 art
2006-05-31 4:18 Zhan, Rongkai
2006-05-31 4:18 ` Zhan, Rongkai
2006-05-31 11:02 art
2006-05-31 11:27 ` Maciej W. Rozycki
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