From: Russell King <rmk+lkml@arm.linux.org.uk>
To: James Bottomley <James.Bottomley@SteelEye.com>
Cc: Tejun Heo <htejun@gmail.com>, Jens Axboe <axboe@suse.de>,
Dave Miller <davem@redhat.com>,
bzolnier@gmail.com, jgarzik@pobox.com, mattjreimer@gmail.com,
Guennadi Liakhovetski <g.liakhovetski@gmx.de>,
lkml <linux-kernel@vger.kernel.org>,
linux-ide@vger.kernel.org, linux-scsi@vger.kernel.org
Subject: Re: [PATCHSET] block: fix PIO cache coherency bug, take 2
Date: Mon, 5 Jun 2006 17:37:52 +0100 [thread overview]
Message-ID: <20060605163752.GE26666@flint.arm.linux.org.uk> (raw)
In-Reply-To: <1149524202.3489.30.camel@mulgrave.il.steeleye.com>
On Mon, Jun 05, 2006 at 11:16:42AM -0500, James Bottomley wrote:
> On Mon, 2006-06-05 at 16:48 +0100, Russell King wrote:
> > When does the zero copy case occur?
>
> Almost all user initiated I/O. Glibc tends to implement this as mmap
> internally.
Ah, so you _are_ talking about something different from what I'm
talking about. I'm concentrating _solely_ on the _read_ side,
and all my responses so far have been concerned about that only.
Anyway, I think this discussion has become meaningless since we've
been talking at cross purposes for the entire thread.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of: 2.6 Serial core
next prev parent reply other threads:[~2006-06-05 16:38 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-06-04 3:41 [PATCHSET] block: fix PIO cache coherency bug, take 2 Tejun Heo
2006-06-04 3:41 ` [PATCH 1/5] arm: implement flush_kernel_dcache_page() Tejun Heo
2006-06-04 3:41 ` Tejun Heo
2006-06-04 3:49 ` [PATCH 1/5] (REPOST) " Tejun Heo
2006-06-04 6:45 ` [PATCH 1/5] " David Miller
2006-06-04 6:53 ` Tejun Heo
2006-06-04 7:04 ` David Miller
2006-06-04 3:41 ` [PATCH 3/5] libata: add cpu cache flushes after kmapping and modifying a page Tejun Heo
2006-06-04 3:41 ` Tejun Heo
2006-06-04 3:41 ` [PATCH 2/5] ide: " Tejun Heo
2006-06-04 3:41 ` Tejun Heo
2006-06-04 8:17 ` Christoph Hellwig
2006-06-04 9:09 ` Tejun Heo
2006-06-04 3:41 ` [PATCH 5/5] md: " Tejun Heo
2006-06-04 3:41 ` Tejun Heo
2006-06-04 3:41 ` [PATCH 4/5] SCSI: " Tejun Heo
2006-06-04 3:41 ` Tejun Heo
2006-06-04 8:20 ` Christoph Hellwig
2006-06-04 9:13 ` Tejun Heo
2006-06-04 20:24 ` Guennadi Liakhovetski
2006-06-04 20:44 ` [PATCHSET] block: fix PIO cache coherency bug, take 2 Russell King
2006-06-04 22:23 ` Russell King
2006-06-05 14:27 ` James Bottomley
2006-06-05 14:44 ` Russell King
2006-06-05 15:24 ` James Bottomley
2006-06-05 15:34 ` Russell King
2006-06-05 15:47 ` James Bottomley
2006-06-05 15:48 ` Russell King
2006-06-05 16:16 ` James Bottomley
2006-06-05 16:37 ` Russell King [this message]
2006-06-05 13:43 ` James Bottomley
2006-06-06 11:00 ` Miklos Szeredi
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