From: Charles Manning <manningc2@actrix.gen.nz>
To: linux-mtd@lists.infradead.org, tglx@linutronix.de
Cc: Steve Finney <saf76@earthlink.net>
Subject: Re: NAND OOB Questions...
Date: Mon, 5 Jun 2006 21:23:47 +1200 [thread overview]
Message-ID: <200606052123.47126.manningc2@actrix.gen.nz> (raw)
In-Reply-To: <1149495264.11983.12.camel@localhost.localdomain>
On Monday 05 June 2006 20:14, Thomas Gleixner wrote:
> On Thu, 2006-06-01 at 09:38 -0700, Steve Finney wrote:
> > 1) The Samsung K9F56* NAND chip allows doing more than one write
> > to the OOB area of a page without an erase; the second write
> > may zero bits that were set to 1 by the first write. Is the Samsung
>
> Bits can not be set to 1 by the first write. FLASH cells are set to 1 by
> erasing and programming can set bits to 0.
>
> > chip unusual in this, or is this normal NAND behavior? (I believe
> > this would be normal for NOR flash).
>
> On NOR you can do this almost unlimited. NAND is much more restricted
> vs. write ordering.
Just one point of clarification that tglx might not have spelled out clearly
here.
In both NAND and NOR you cannot set a 0 bit back to a 1 bit by programming.
You can only do this by erasing the erasable block.
Where NOR and NAND differ is that if you program a pattern into NOR that tries
to set a 0 to a 1 then (in most cases) the programming operation will be
aborted. However, NAND will program the zeros only and 1 bits are just "don't
care".
next prev parent reply other threads:[~2006-06-05 9:15 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-06-01 16:38 NAND OOB Questions Steve Finney
2006-06-05 8:14 ` Thomas Gleixner
2006-06-05 9:23 ` Charles Manning [this message]
[not found] <21148625.1149520632350.JavaMail.root@elwamui-karabash.atl.sa.earthlink.net>
2006-06-06 5:38 ` Thomas Gleixner
[not found] <15200571.1149603155027.JavaMail.root@elwamui-darkeyed.atl.sa.earthlink.net>
2006-06-06 15:03 ` Thomas Gleixner
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