From: Thiemo Seufer <ths@networkno.de>
To: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
Subject: [PATCH] Improve interrupt latency again for sb1250/bcm1480
Date: Wed, 5 Jul 2006 14:26:38 +0100 [thread overview]
Message-ID: <20060705132638.GC29112@networkno.de> (raw)
Hello All,
this patch restores the behaviour of the old (assembly-written)
interrupt handler, the handler is left as soon as a single interrupt
cause is handled.
Thiemo
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 0eb0b10..ed325f0 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -502,22 +502,23 @@ #endif
#ifdef CONFIG_SIBYTE_BCM1480_PROF
if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
sbprof_cpu_intr(exception_epc(regs));
+ else
#endif
if (pending & CAUSEF_IP4)
bcm1480_timer_interrupt(regs);
#ifdef CONFIG_SMP
- if (pending & CAUSEF_IP3)
+ else if (pending & CAUSEF_IP3)
bcm1480_mailbox_interrupt(regs);
#endif
#ifdef CONFIG_KGDB
- if (pending & CAUSEF_IP6)
+ else if (pending & CAUSEF_IP6)
bcm1480_kgdb_interrupt(regs); /* KGDB (uart 1) */
#endif
- if (pending & CAUSEF_IP2) {
+ else if (pending & CAUSEF_IP2) {
unsigned long long mask_h, mask_l;
unsigned long base;
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 8d49cb5..1de71ad 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -460,25 +460,25 @@ #endif
pending = read_c0_cause();
#ifdef CONFIG_SIBYTE_SB1250_PROF
- if (pending & CAUSEF_IP7) { /* Cpu performance counter interrupt */
+ if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
sbprof_cpu_intr(exception_epc(regs));
- }
+ else
#endif
if (pending & CAUSEF_IP4)
sb1250_timer_interrupt(regs);
#ifdef CONFIG_SMP
- if (pending & CAUSEF_IP3)
+ else if (pending & CAUSEF_IP3)
sb1250_mailbox_interrupt(regs);
#endif
#ifdef CONFIG_KGDB
- if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
+ else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
sb1250_kgdb_interrupt(regs);
#endif
- if (pending & CAUSEF_IP2) {
+ else if (pending & CAUSEF_IP2) {
unsigned long long mask;
/*
reply other threads:[~2006-07-05 13:26 UTC|newest]
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