[U-Boot-Users] [PATCH] au1x00 LCD support

[Rodolfo Giometti <giometti@linux.it>]

On Wed, Jul 12, 2006 at 07:48:47PM +0200, Wolfgang Denk wrote:
> 
> So what's that? DO you think I will manually unindent  your  posting?
> I won't. Please repost your original patch after cleaning it up.

CHANGELOG:

LCD support for au1x00 CPUs.

NOTE:

Tested on a AU1100 based board.

Signed-off-by: Rodolfo Giometti <giometti@linux.it>

Ciao,

Rodolfo

-- 

GNU/Linux Solutions                  e-mail:    giometti at enneenne.com
Linux Device Driver                             giometti at gnudd.com
Embedded Systems                     		giometti at linux.it
UNIX programming                     phone:     +39 349 2432127
-------------- next part --------------
diff --git a/common/lcd.c b/common/lcd.c
index 9d00585..f6065f8 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -42,7 +42,7 @@ #endif
 #include <lcd.h>
 #include <watchdog.h>
 
-#if defined(CONFIG_PXA250)
+#if defined(CONFIG_PXA250) || defined(CONFIG_AU1X00)
 #include <asm/byteorder.h>
 #endif
 
@@ -62,7 +62,7 @@ #include <video_font.h>		/* Get font dat
 /************************************************************************/
 #ifdef CONFIG_LCD_LOGO
 # include <bmp_logo.h>		/* Get logo data, width and height	*/
-# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
+# if (LCD_BPP < LCD_COLOR16) && (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET)
 #  error Default Color Map overlaps with Logo Color Map
 # endif
 #endif
@@ -512,16 +512,19 @@ static int lcd_getbgcolor (void)
 #ifdef CONFIG_LCD_LOGO
 void bitmap_plot (int x, int y)
 {
-	ushort *cmap;
 	ushort i, j;
 	uchar *bmap;
 	uchar *fb;
 	ushort *fb16;
 #if defined(CONFIG_PXA250)
+	ushort *cmap;
 	struct pxafb_info *fbi = &panel_info.pxa;
 #elif defined(CONFIG_MPC823)
+	ushort *cmap;
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile cpm8xx_t *cp = &(immr->im_cpm);
+#elif defined(CONFIG_AU1X00)
+	uint *cmap;
 #endif
 
 	debug ("Logo: width %d  height %d  colors %d  cmap %d\n",
@@ -537,6 +540,8 @@ #if defined(CONFIG_PXA250)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
+#elif defined(CONFIG_AU1X00)
+		cmap = (u_int *)panel_info.palette+BMP_LOGO_OFFSET*sizeof(uint);
 #endif
 
 		WATCHDOG_RESET();
@@ -582,7 +587,6 @@ #if (CONFIG_COMMANDS & CFG_CMD_BMP) || d
  */
 int lcd_display_bitmap(ulong bmp_image, int x, int y)
 {
-	ushort *cmap;
 	ushort i, j;
 	uchar *fb;
 	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
@@ -593,9 +597,13 @@ int lcd_display_bitmap(ulong bmp_image, 
 	unsigned long compression;
 #if defined(CONFIG_PXA250)
 	struct pxafb_info *fbi = &panel_info.pxa;
+	ushort *cmap;
 #elif defined(CONFIG_MPC823)
 	volatile immap_t *immr = (immap_t *) CFG_IMMR;
 	volatile cpm8xx_t *cp = &(immr->im_cpm);
+	ushort *cmap;
+#elif defined(CONFIG_AU1X00)
+	u_int *cmap;
 #endif
 
 	if (!((bmp->header.signature[0]=='B') &&
@@ -632,6 +640,8 @@ #if defined(CONFIG_PXA250)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
+#elif defined(CONFIG_AU1X00)
+		cmap = (u_int *)panel_info.palette;
 #else
 # error "Don't know location of color map"
 #endif
@@ -648,7 +658,7 @@ #ifdef CFG_INVERT_COLORS
 #else
 			*cmap = colreg;
 #endif
-#if defined(CONFIG_PXA250)
+#if defined(CONFIG_PXA250) || defined(CONFIG_AU1X00)
 			cmap++;
 #elif defined(CONFIG_MPC823)
 			cmap--;
@@ -668,7 +678,7 @@ #endif
 	for (i = 0; i < height; ++i) {
 		WATCHDOG_RESET();
 		for (j = 0; j < width ; j++)
-#if defined(CONFIG_PXA250)
+#if defined(CONFIG_PXA250) || defined(CONFIG_AU1X00)
 			*(fb++)=*(bmap++);
 #elif defined(CONFIG_MPC823)
 			*(fb++)=255-*(bmap++);
diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
index c8b30c7..497bcd6 100644
--- a/cpu/mips/Makefile
+++ b/cpu/mips/Makefile
@@ -27,7 +27,7 @@ LIB	= lib$(CPU).a
 
 START	= start.o
 OBJS	= asc_serial.o au1x00_serial.o au1x00_eth.o au1x00_usb_ohci.o \
-	  cpu.o interrupts.o incaip_clock.o
+	  au1x00_fb.o cpu.o interrupts.o incaip_clock.o
 SOBJS	= incaip_wdt.o cache.o
 
 all:	.depend $(START) $(LIB)
diff --git a/cpu/mips/au1x00_fb.c b/cpu/mips/au1x00_fb.c
new file mode 100644
index 0000000..b007683
--- /dev/null
+++ b/cpu/mips/au1x00_fb.c
@@ -0,0 +1,262 @@
+/*
+ * AU1x00 LCD Controller
+ *
+ * (C) Copyright 2006
+ * Rodolfo Giometti <giometti@linux.it>
+ * Eurotech S.p.A. <info@eurotech.it>
+ *
+ * Strongly based on "linux/drivers/video/au1100fb.c" by
+ * Embedded Alley Solutions and others.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <common.h>
+#include <version.h>
+#include <stdarg.h>
+#include <linux/types.h>
+#include <devices.h>
+#include <lcd.h>
+
+#include <asm-mips/au1x00.h>
+#include <asm-mips/io.h>
+#include <asm-mips/addrspace.h>
+
+#define DEBUG
+
+#ifdef CONFIG_LCD
+
+/* --- Define panel info video struct for your display ----------------------*/
+
+#ifdef CONFIG_TD035STED4
+
+/* 320x240x16 */
+#define DISPLAY_COL	320
+#define DISPLAY_ROW	240
+#define DISPLAY_BPP	LCD_COLOR16
+vidinfo_t panel_info = {
+	.vl_col		= DISPLAY_COL,
+	.vl_row		= DISPLAY_ROW,
+	.vl_bpix	= DISPLAY_BPP,
+
+	.vl_clor	= 1,
+	.vl_tft		= 1,
+
+	.control_base	=
+		( LCD_CONTROL_BPP_16
+		| LCD_CONTROL_PC | LCD_CONTROL_C | LCD_CONTROL_PT
+		| LCD_CONTROL_PO_00 | LCD_CONTROL_SM_90
+		| LCD_CONTROL_SBPPF_565 ),
+	.horztiming =
+		( LCD_HORZTIMING_HN2_N(10)
+		| LCD_HORZTIMING_HN1_N(20)
+		| LCD_HORZTIMING_HPW_N(10)
+		| LCD_HORZTIMING_PPL_N(DISPLAY_ROW) ),
+	.verttiming =
+		( LCD_VERTTIMING_VN2_N(5)
+		| LCD_VERTTIMING_VN1_N(1)
+		| LCD_VERTTIMING_VPW_N(1)
+		| LCD_VERTTIMING_LPP_N(DISPLAY_COL) ),
+	.clkcontrol_base =
+		( LCD_CLKCONTROL_PCD_N(1)
+		| LCD_CLKCONTROL_IH ),
+};
+#endif /* CONFIG_TOPPOLY_TD035STED4 */
+#if LCD_BPP != DISPLAY_BPP
+# error "Invalid BPP mode for selected display"
+#endif
+
+/* --- Global variables ---------------------------------------------------- */
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+void *lcd_base;				/* Start of framebuffer memory	*/
+void *lcd_console_address;		/* Start of console buffer	*/
+
+short console_col;
+short console_row;
+
+/* --- AU1X000 specific functions ------------------------------------------ */
+
+static int au1x00fb_mem_setup(void *lcdbase, vidinfo_t *vid)
+{
+	vid->screen = (u_long) lcdbase;
+	vid->screen_size = vid->vl_row * (vid->vl_col * NBITS(vid->vl_bpix)) / 8;
+	vid->palette = LCD_PALLETTEBASE;
+
+	debug("screen:		0x%08lx\n", (u_long) vid->screen);
+	debug("screen_size:	0x%08lx\n", (u_long) vid->screen_size);
+	debug("palette:		0x%08lx\n", (u_long) vid->palette);
+
+	return 0;
+}
+
+static void au1x00fb_setup_gpio(vidinfo_t *vid)
+{
+	/* Setup LCD pins functionality */
+	au_writel(au_readl(SYS_PINFUNC)|SYS_PF_LCD, SYS_PINFUNC);
+
+#ifdef CONFIG_WWPC
+	/* Init the GPIOs for LCD stuff */
+	/* We need:
+	 *    GPIO  19 (PANEL SHUTDOWN) as OUTPUT default to 0
+	 *    GPIO  7  (PANEL ENABLE) as OUTPUT default to 0
+	 */
+	au_writel(WWPC_GPIO_PANEL_SD|WWPC_GPIO_PANEL_ENABLE, SYS_OUTPUTCLR);
+#endif
+}
+
+static int au1x00fb_init(vidinfo_t *vid)
+{
+	u_int sys_clksrc, sys_freqctrl1, line_len, words;
+
+	/* Setup LCD clock to AUX (48 MHz) */
+#ifdef CONFIG_WWPC
+	sys_freqctrl1 = au_readl(SYS_FREQCTRL1)&~(0x3ff);
+	sys_freqctrl1 |= (1<<1)|(1<<4)|(1<<3)|(1<<2);
+	au_writel(sys_freqctrl1, SYS_FREQCTRL1);
+
+	sys_clksrc = au_readl(SYS_CLKSRC);
+	sys_clksrc &= ~(SYS_CS_ML_MASK|SYS_CS_DL);
+	sys_clksrc |= 5<<SYS_CS_ML_BIT;
+	au_writel(sys_clksrc, SYS_CLKSRC);
+#else
+	sys_clksrc = au_readl(SYS_CLKSRC) & ~(SYS_CS_ML_MASK | SYS_CS_DL | SYS_CS_CL);
+	au_writel((sys_clksrc | (1 << SYS_CS_ML_BIT)), SYS_CLKSRC);
+#endif
+
+	/* Set h/w registers */
+	au_writel(vid->control_base, LCD_CONTROL);
+	au_writel(0, LCD_INTENABLE);
+	au_writel(0, LCD_INTSTATUS);
+	au_writel(vid->horztiming, LCD_HORZTIMING);
+	au_writel(vid->verttiming, LCD_VERTTIMING);
+	au_writel(vid->clkcontrol_base, LCD_CLKCONTROL);
+	au_writel(virt_to_phys(vid->screen), LCD_DMAADDR0);
+
+	line_len = vid->vl_col * NBITS(vid->vl_bpix) / 8;
+	words = line_len / sizeof(u32);
+	if ((vid->control_base & LCD_CONTROL_SM_0) || 
+	    (vid->control_base & LCD_CONTROL_SM_180)) {
+		words *= vid->vl_row;
+		if (vid->control_base & LCD_CONTROL_SM_180)
+			words -= (words % 8); /* should be divisable by 8 */
+	}
+	au_writel(words-1, LCD_WORDS);
+
+	au_writel(0, LCD_PWMDIV);
+	au_writel(0, LCD_PWMHI);
+
+	au_sync();
+
+	debug("LCD_CONTROL:	%x\n", au_readl(LCD_CONTROL));
+	debug("LCD_INTSTATUS:	%x\n", au_readl(LCD_INTSTATUS));
+	debug("LCD_INTENABLE:	%x\n", au_readl(LCD_INTENABLE));
+	debug("LCD_HORZTIMING:	%x\n", au_readl(LCD_HORZTIMING));
+	debug("LCD_VERTTIMING:	%x\n", au_readl(LCD_VERTTIMING));
+	debug("LCD_CLKCONTROL:	%x\n", au_readl(LCD_CLKCONTROL));
+	debug("LCD_DMAADDR0:	%x\n", au_readl(LCD_DMAADDR0));
+	debug("LCD_DMAADDR1:	%x\n", au_readl(LCD_DMAADDR1));
+	debug("LCD_WORDS:	%x\n", au_readl(LCD_WORDS));
+	debug("LCD_PWMDIV:	%x\n", au_readl(LCD_PWMDIV));
+	debug("LCD_PWMHI:	%x\n", au_readl(LCD_PWMHI));
+
+	return 0;
+}
+
+static void au1x00fb_enable_controller(vidinfo_t *vid)
+{
+	u_int lcd_control;
+
+	/* Turn on panel */
+#ifdef CONFIG_WWPC
+	au_writel(WWPC_GPIO_PANEL_ENABLE, SYS_OUTPUTSET);
+	au_writel(WWPC_GPIO_PANEL_SD, SYS_OUTPUTSET);
+#endif
+
+	lcd_control = au_readl(LCD_CONTROL);
+	au_writel(lcd_control | LCD_CONTROL_GO, LCD_CONTROL);
+
+	au_sync();
+}
+
+/* --- Public functions ---------------------------------------------------- */
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+	u_int value = 0;
+
+	debug("%s\n", __FUNCTION__);
+printf("LCD_SETCOLREG REG %d R %d G %d B %d\n", regno, red, green, blue);
+
+	if (regno > 255) {
+		printf("%s: invalid palette regno %d\n", __FUNCTION__, regno);
+		return;
+	}
+
+	if (!panel_info.vl_clor) {
+		/* Convert color to grayscale */
+		red = green = blue = 
+			(19595 * red + 38470 * green + 7471 * blue) >> 16;
+	}
+
+	if (panel_info.vl_clor) {
+		/* Color panel */
+		debug("%s: color mode\n", __FUNCTION__);
+
+		if (panel_info.control_base & LCD_CONTROL_SBPPF_565)
+			value = ((red   << 8) & 0xF800)| \
+				((green << 3) & 0x07E0)| \
+				((blue  << 0) & 0x001F);
+		else
+			printf("%s: warning! Unsupported RGB scheme!\n", __FUNCTION__);
+		value &= 0xFFFF;
+printf("VAL %x\n", value);
+	} else {
+		/* MONOCHROME MODE */
+		debug("%s: monocrome mode\n", __FUNCTION__);
+
+		value = (green >> 12) & 0x000F;
+		value &= 0xF;
+	}
+
+	printf("LCD_SETCOLREG addr %x value %x\n", LCD_PALLETTEBASE+regno*4, value);
+	au_writel(value, LCD_PALLETTEBASE+regno*4);
+
+	debug("%s: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", __FUNCTION__,
+		regno, &palette[regno],
+		red, green, blue,
+		palette[regno]);
+}
+
+void lcd_enable(void)
+{
+	debug("%s: nothing to do here...\n", __FUNCTION__);
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	au1x00fb_mem_setup(lcdbase, &panel_info);
+	au1x00fb_setup_gpio(&panel_info);
+	au1x00fb_init(&panel_info);
+	au1x00fb_enable_controller(&panel_info);
+}
+
+#endif /* CONFIG_LCD */
diff --git a/include/asm-mips/au1x00.h b/include/asm-mips/au1x00.h
index 4e19dc4..c906a09 100644
--- a/include/asm-mips/au1x00.h
+++ b/include/asm-mips/au1x00.h
@@ -829,6 +829,147 @@ #define SSI_ENABLE_CD				(1<<1)
 #define SSI_ENABLE_E				(1<<0)
 
 
+/* LCD Controller */
+#define LCD_CONTROL		  0xB5000000
+  #define LCD_CONTROL_SBB_BIT      21
+  #define LCD_CONTROL_SBB_MASK     (0x3 << LCD_CONTROL_SBB_BIT)
+    #define LCD_CONTROL_SBB_1        (0 << LCD_CONTROL_SBB_BIT)
+    #define LCD_CONTROL_SBB_2        (1 << LCD_CONTROL_SBB_BIT)
+    #define LCD_CONTROL_SBB_3        (2 << LCD_CONTROL_SBB_BIT)
+    #define LCD_CONTROL_SBB_4        (3 << LCD_CONTROL_SBB_BIT)
+  #define LCD_CONTROL_SBPPF_BIT    18
+  #define LCD_CONTROL_SBPPF_MASK   (0x7 << LCD_CONTROL_SBPPF_BIT)
+    #define LCD_CONTROL_SBPPF_655    (0 << LCD_CONTROL_SBPPF_BIT)
+    #define LCD_CONTROL_SBPPF_565    (1 << LCD_CONTROL_SBPPF_BIT)
+    #define LCD_CONTROL_SBPPF_556    (2 << LCD_CONTROL_SBPPF_BIT)
+    #define LCD_CONTROL_SBPPF_1555   (3 << LCD_CONTROL_SBPPF_BIT)
+    #define LCD_CONTROL_SBPPF_5551   (4 << LCD_CONTROL_SBPPF_BIT)
+  #define LCD_CONTROL_WP           (1<<17)
+  #define LCD_CONTROL_WD           (1<<16)
+  #define LCD_CONTROL_C            (1<<15)
+  #define LCD_CONTROL_SM_BIT       13
+  #define LCD_CONTROL_SM_MASK      (0x3 << LCD_CONTROL_SM_BIT)
+    #define LCD_CONTROL_SM_0         (0 << LCD_CONTROL_SM_BIT)
+    #define LCD_CONTROL_SM_90        (1 << LCD_CONTROL_SM_BIT)
+    #define LCD_CONTROL_SM_180       (2 << LCD_CONTROL_SM_BIT)
+    #define LCD_CONTROL_SM_270       (3 << LCD_CONTROL_SM_BIT)
+  #define LCD_CONTROL_DB           (1<<12)
+  #define LCD_CONTROL_CCO          (1<<11)
+  #define LCD_CONTROL_DP           (1<<10)
+  #define LCD_CONTROL_PO_BIT       8
+  #define LCD_CONTROL_PO_MASK      (0x3 << LCD_CONTROL_PO_BIT)
+    #define LCD_CONTROL_PO_00        (0 << LCD_CONTROL_PO_BIT)
+    #define LCD_CONTROL_PO_01        (1 << LCD_CONTROL_PO_BIT)
+    #define LCD_CONTROL_PO_10        (2 << LCD_CONTROL_PO_BIT)
+    #define LCD_CONTROL_PO_11        (3 << LCD_CONTROL_PO_BIT)
+  #define LCD_CONTROL_MPI          (1<<7)
+  #define LCD_CONTROL_PT           (1<<6)
+  #define LCD_CONTROL_PC           (1<<5)
+  #define LCD_CONTROL_BPP_BIT      1
+  #define LCD_CONTROL_BPP_MASK     (0x7 << LCD_CONTROL_BPP_BIT)
+    #define LCD_CONTROL_BPP_1        (0 << LCD_CONTROL_BPP_BIT)
+    #define LCD_CONTROL_BPP_2        (1 << LCD_CONTROL_BPP_BIT)
+    #define LCD_CONTROL_BPP_4        (2 << LCD_CONTROL_BPP_BIT)
+    #define LCD_CONTROL_BPP_8        (3 << LCD_CONTROL_BPP_BIT)
+    #define LCD_CONTROL_BPP_12       (4 << LCD_CONTROL_BPP_BIT)
+    #define LCD_CONTROL_BPP_16       (5 << LCD_CONTROL_BPP_BIT)
+  #define LCD_CONTROL_GO           (1<<0)
+
+#define LCD_INTSTATUS		  0xB5000004
+#define LCD_INTENABLE		  0xB5000008
+  #define LCD_INT_SD               (1<<7)
+  #define LCD_INT_OF               (1<<6)
+  #define LCD_INT_UF               (1<<5)
+  #define LCD_INT_SA               (1<<3)
+  #define LCD_INT_SS               (1<<2)
+  #define LCD_INT_S1               (1<<1)
+  #define LCD_INT_S0               (1<<0)
+
+#define LCD_HORZTIMING		  0xB500000C
+  #define LCD_HORZTIMING_HN2_BIT   24
+  #define LCD_HORZTIMING_HN2_MASK  (0xFF << LCD_HORZTIMING_HN2_BIT)
+  #define LCD_HORZTIMING_HN2_N(N)  ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
+  #define LCD_HORZTIMING_HN1_BIT   16
+  #define LCD_HORZTIMING_HN1_MASK  (0xFF << LCD_HORZTIMING_HN1_BIT)
+  #define LCD_HORZTIMING_HN1_N(N)  ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
+  #define LCD_HORZTIMING_HPW_BIT   10
+  #define LCD_HORZTIMING_HPW_MASK  (0x3F << LCD_HORZTIMING_HPW_BIT)
+  #define LCD_HORZTIMING_HPW_N(N)  ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
+  #define LCD_HORZTIMING_PPL_BIT   0
+  #define LCD_HORZTIMING_PPL_MASK  (0x3FF << LCD_HORZTIMING_PPL_BIT)
+  #define LCD_HORZTIMING_PPL_N(N)  ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
+
+#define LCD_VERTTIMING		  0xB5000010
+  #define LCD_VERTTIMING_VN2_BIT   24
+  #define LCD_VERTTIMING_VN2_MASK  (0xFF << LCD_VERTTIMING_VN2_BIT)
+  #define LCD_VERTTIMING_VN2_N(N)  ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
+  #define LCD_VERTTIMING_VN1_BIT   16
+  #define LCD_VERTTIMING_VN1_MASK  (0xFF << LCD_VERTTIMING_VN1_BIT)
+  #define LCD_VERTTIMING_VN1_N(N)  ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
+  #define LCD_VERTTIMING_VPW_BIT   10
+  #define LCD_VERTTIMING_VPW_MASK  (0x3F << LCD_VERTTIMING_VPW_BIT)
+  #define LCD_VERTTIMING_VPW_N(N)  ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
+  #define LCD_VERTTIMING_LPP_BIT   0
+  #define LCD_VERTTIMING_LPP_MASK  (0x3FF << LCD_VERTTIMING_LPP_BIT)
+  #define LCD_VERTTIMING_LPP_N(N)  ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
+
+#define LCD_CLKCONTROL		  0xB5000014
+  #define LCD_CLKCONTROL_IB        (1<<18)
+  #define LCD_CLKCONTROL_IC        (1<<17)
+  #define LCD_CLKCONTROL_IH        (1<<16)
+  #define LCD_CLKCONTROL_IV        (1<<15)
+  #define LCD_CLKCONTROL_BF_BIT    10
+  #define LCD_CLKCONTROL_BF_MASK   (0x1F << LCD_CLKCONTROL_BF_BIT)
+  #define LCD_CLKCONTROL_BF_N(N)   ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
+  #define LCD_CLKCONTROL_PCD_BIT   0
+  #define LCD_CLKCONTROL_PCD_MASK  (0x3FF << LCD_CLKCONTROL_PCD_BIT)
+  #define LCD_CLKCONTROL_PCD_N(N)  (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
+
+#define LCD_DMAADDR0		  0xB5000018
+#define LCD_DMAADDR1		  0xB500001C
+  #define LCD_DMA_SA_BIT           5
+  #define LCD_DMA_SA_MASK          (0x7FFFFFF << LCD_DMA_SA_BIT)
+  #define LCD_DMA_SA_N(N)          ((N) & LCD_DMA_SA_MASK)
+
+#define LCD_WORDS		  0xB5000020
+  #define LCD_WRD_WRDS_BIT         0
+  #define LCD_WRD_WRDS_MASK        (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
+  #define LCD_WRD_WRDS_N(N)        ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
+
+#define LCD_PWMDIV		  0xB5000024
+  #define LCD_PWMDIV_EN            (1<<12)
+  #define LCD_PWMDIV_PWMDIV_BIT    0
+  #define LCD_PWMDIV_PWMDIV_MASK   (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
+  #define LCD_PWMDIV_PWMDIV_N(N)   ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
+
+#define LCD_PWMHI		  0xB5000028
+  #define LCD_PWMHI_PWMHI1_BIT     12
+  #define LCD_PWMHI_PWMHI1_MASK    (0xFFF << LCD_PWMHI_PWMHI1_BIT)
+  #define LCD_PWMHI_PWMHI1_N(N)    (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
+  #define LCD_PWMHI_PWMHI0_BIT     0
+  #define LCD_PWMHI_PWMHI0_MASK    (0xFFF << LCD_PWMHI_PWMHI0_BIT)
+  #define LCD_PWMHI_PWMHI0_N(N)    (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
+
+#define LCD_PALLETTEBASE	  0xB5000400
+  #define LCD_PALLETTE_MONO_MI_BIT      0
+  #define LCD_PALLETTE_MONO_MI_MASK     (0xF << LCD_PALLETTE_MONO_MI_BIT)
+  #define LCD_PALLETTE_MONO_MI_N(N)     (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
+
+  #define LCD_PALLETTE_COLOR_RI_BIT     8
+  #define LCD_PALLETTE_COLOR_RI_MASK    (0xF << LCD_PALLETTE_COLOR_RI_BIT)
+  #define LCD_PALLETTE_COLOR_RI_N(N)    (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
+  #define LCD_PALLETTE_COLOR_GI_BIT     4
+  #define LCD_PALLETTE_COLOR_GI_MASK    (0xF << LCD_PALLETTE_COLOR_GI_BIT)
+  #define LCD_PALLETTE_COLOR_GI_N(N)    (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
+  #define LCD_PALLETTE_COLOR_BI_BIT     0
+  #define LCD_PALLETTE_COLOR_BI_MASK    (0xF << LCD_PALLETTE_COLOR_BI_BIT)
+  #define LCD_PALLETTE_COLOR_BI_N(N)    (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
+
+  #define LCD_PALLETTE_TFT_DC_BIT       0
+  #define LCD_PALLETTE_TFT_DC_MASK      (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
+  #define LCD_PALLETTE_TFT_DC_N(N)      (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
+
+
 /* IrDA Controller */
 #define IRDA_BASE                 0xB0300000
 #define IR_RING_PTR_STATUS        (IRDA_BASE+0x00)
@@ -886,6 +1027,13 @@ #define SYS_PF_U0			(1<<3)	/* U0TXD/GPIO
 #define SYS_PF_RD			(1<<2)	/* IRTXD/GPIO19 */
 #define SYS_PF_A97			(1<<1)	/* AC97/SSL1 */
 #define SYS_PF_S0			(1<<0)	/* SSI_0/GPIO[16:18] */
+
+/* Au1100 Only */
+#define SYS_PF_PC			(1<<18) /* PCMCIA/GPIO[207:204] */
+#define SYS_PF_LCD			(1<<17) /* extern lcd/GPIO[203:200] */
+#define SYS_PF_CS			(1<<16) /* EXTCLK0/32khz to gpio2 */
+#define SYS_PF_EX0			(1<<9)  /* gpio2/clock */
+
 #define SYS_TRIOUTRD              0xB1900100
 #define SYS_TRIOUTCLR             0xB1900100
 #define SYS_OUTPUTRD              0xB1900108
@@ -952,6 +1100,12 @@ #define SYS_CS_MI2_BIT            17
 #define SYS_CS_MI2_MASK           (0x7<<CSC_MI2_BIT)
 #define SYS_CS_DI2                (1<<16)
 #define SYS_CS_CI2                (1<<15)
+#ifdef CONFIG_AU1100
+#define SYS_CS_ML_BIT             7
+#define SYS_CS_ML_MASK            (0x7<<SYS_CS_ML_BIT)
+#define SYS_CS_DL                 (1<<6)
+#define SYS_CS_CL                 (1<<5)
+#else
 #define SYS_CS_MUH_BIT            12
 #define SYS_CS_MUH_MASK           (0x7<<CSC_MUH_BIT)
 #define SYS_CS_DUH                (1<<11)
@@ -960,6 +1114,7 @@ #define SYS_CS_MUD_BIT            7
 #define SYS_CS_MUD_MASK           (0x7<<CSC_MUD_BIT)
 #define SYS_CS_DUD                (1<<6)
 #define SYS_CS_CUD                (1<<5)
+#endif
 #define SYS_CS_MIR_BIT            2
 #define SYS_CS_MIR_MASK           (0x7<<CSC_MIR_BIT)
 #define SYS_CS_DIR                (1<<1)
diff --git a/include/asm-mips/global_data.h b/include/asm-mips/global_data.h
index a024194..d1e39bf 100644
--- a/include/asm-mips/global_data.h
+++ b/include/asm-mips/global_data.h
@@ -45,6 +45,7 @@ typedef	struct	global_data {
 	unsigned long	reloc_off;	/* Relocation Offset */
 	unsigned long	env_addr;	/* Address  of Environment struct */
 	unsigned long	env_valid;	/* Checksum of Environment valid? */
+	unsigned long	fb_base;	/* base address of frame buffer */
 	void		**jt;		/* jump table */
 } gd_t;
 
diff --git a/include/lcd.h b/include/lcd.h
index 7e23736..e3a9cd4 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -148,7 +148,38 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
-#endif /* CONFIG_MPC823 or CONFIG_PXA250 */
+#elif defined CONFIG_AU1X00
+
+/*
+ * LCD controller stucture for AU1X00 CPU
+ */
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 640) */
+	ushort	vl_row;		/* Number of rows (i.e. 480) */
+
+	/* LCD configuration register */
+	u_char	vl_bpix;		/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_char	vl_clor;	/* 0 = monocrome, 1 = color */
+	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
+
+	/* Control register. Timing from data sheet */
+	u_long	control_base;
+	u_long	horztiming;
+	u_long	verttiming;
+	u_long	clkcontrol_base;
+
+	/* DMA registers */
+	u_long	dma_addr0;
+	u_long	dma_addr1;
+
+	u_long	screen;		/* physical address of frame buffer */
+	u_long	screen_size;
+	u_long	palette;	/* physical address of palette table */
+} vidinfo_t;
+
+extern vidinfo_t panel_info;
+
+#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_AU1X00 */
 
 /* Video functions */
 
@@ -198,8 +229,10 @@ # define LCD_INFO_Y		(VIDEO_FONT_HEIGHT)
 #endif
 
 /* Default to 8bpp if bit depth not specified */
-#ifndef LCD_BPP
-# define LCD_BPP			LCD_COLOR8
+#ifndef CONFIG_LCD_BPP
+# define LCD_BPP		LCD_COLOR8
+#else
+# define LCD_BPP		CONFIG_LCD_BPP
 #endif
 #ifndef LCD_DF
 # define LCD_DF			1
@@ -241,6 +274,13 @@ #else
  * 16bpp color definitions
  */
 # define CONSOLE_COLOR_BLACK	0x0000
+# define CONSOLE_COLOR_RED	0xf800
+# define CONSOLE_COLOR_GREEN	0x07e0
+# define CONSOLE_COLOR_YELLOW	0xffe0
+# define CONSOLE_COLOR_BLUE	0x001f
+# define CONSOLE_COLOR_MAGENTA	0xf81f
+# define CONSOLE_COLOR_CYAN	0x07ff
+# define CONSOLE_COLOR_GREY	0xad4a
 # define CONSOLE_COLOR_WHITE	0xffff	/* Must remain last / highest	*/
 
 #endif /* color definitions */
@@ -272,7 +312,7 @@ #define CONSOLE_SCROLL_SIZE	(CONSOLE_SIZ
 #if LCD_BPP == LCD_MONOCHROME
 # define COLOR_MASK(c)		((c)	  | (c) << 1 | (c) << 2 | (c) << 3 | \
 				 (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
-#elif LCD_BPP == LCD_COLOR8
+#elif LCD_BPP == LCD_COLOR8 || LCD_BPP == LCD_COLOR16
 # define COLOR_MASK(c)		(c)
 #else
 # error Unsupported LCD BPP.
diff --git a/lib_mips/board.c b/lib_mips/board.c
index b7d3356..dcfc0d7 100644
--- a/lib_mips/board.c
+++ b/lib_mips/board.c
@@ -213,6 +213,12 @@ #endif
 	addr &= ~(4096 - 1);
 	debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
 
+#if defined(CONFIG_LCD)
+	/* Reserve memory for LCD display (always full pages) */
+	addr = lcd_setmem (addr);
+	gd->fb_base = addr;
+#endif
+
 	/* Reserve memory for U-Boot code, data & bss
 	 * round down to next 16 kB limit
 	 */
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