From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GDQBG-0007C0-St for qemu-devel@nongnu.org; Wed, 16 Aug 2006 14:31:54 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GDQBE-0007Aj-2q for qemu-devel@nongnu.org; Wed, 16 Aug 2006 14:31:53 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GDQBD-0007Ag-TZ for qemu-devel@nongnu.org; Wed, 16 Aug 2006 14:31:51 -0400 Received: from [193.7.176.20] (helo=bender.bawue.de) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.52) id 1GDQHX-0000Vo-9O for qemu-devel@nongnu.org; Wed, 16 Aug 2006 14:38:23 -0400 Received: from lagash (mipsfw.mips-uk.com [194.74.144.146]) (using TLSv1 with cipher DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by bender.bawue.de (Postfix) with ESMTP id 8027F46327 for ; Wed, 16 Aug 2006 20:30:31 +0200 (MEST) Received: from ths by lagash with local (Exim 4.62) (envelope-from ) id 1GDQ8b-0003Mk-6L for qemu-devel@nongnu.org; Wed, 16 Aug 2006 19:29:09 +0100 Date: Wed, 16 Aug 2006 19:29:09 +0100 Subject: Re: [Qemu-devel] Wrong reset of MIPS hflags EXL after interrupt? Message-ID: <20060816182908.GC6387@networkno.de> References: <44E3500A.4050608@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <44E3500A.4050608@gmail.com> From: Thiemo Seufer Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Dirk Behme wrote: > Hi, > > I'm not sure, but while playing with MIPS interrupts, it > seems to me that something with reset of interrupt flag > MIPS_HFLAG_EXL (0x04) at exception exit (eret) is wrong. It > seems to me that only one interrupt is executed because > after eret, MIPS_HFLAG_EXL stays set in env->hflags. Then, > at next interrupt, system correctly checks for > MIPS_HFLAG_EXL, but this is still set and no further > interrupt happens. This explains some weirdness I saw on my hacked up qemu when running a mips32r2-compiled Linux kernel. > Debugging shows that op_eret() in MIPS op.c correctly reset > this bit: env->hflags &= ~MIPS_HFLAG_EXL; But debug output > at end of e.g. save_cpu_state() (debug output of ctx->hflags > and ctx->saved_hflags ) or in function which tries to issue > (next) timer interrupt (debug output of env->hflags) > MIPS_HFLAG_EXL is still (again?) set everywhere. Looks like > the correct env->hflags from op_eret() is overwritten > somewhere later with wrong value. > > These three ctx->hflags, ctx->saved_hflags and env->hflags > are confusing me ;) Where are they synchronized after eret? > Or who overwrites the env->hflags correctly set by eret > again? Any ideas, why eret sets env->hflags correctly and > later global env->hflags has still/again wrong value? Any > other hints? AFAIU qemu maintains an environment stack, I guess popping the environment restores the old flag contents. Thiemo