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Date:	Mon, 11 Sep 2006 16:17:34 +0100
From:	Thiemo Seufer <ths@networkno.de>
To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc:	nigel@mips.com, ralf@linux-mips.org, dan@debian.org,
	macro@linux-mips.org, linux-mips@linux-mips.org
Subject: Re: [PATCH] fast path for rdhwr emulation for TLS
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References: <20060911.140403.126141483.nemoto@toshiba-tops.co.jp> <20060911.175029.37531637.nemoto@toshiba-tops.co.jp> <20060911094905.GB13414@networkno.de> <20060911.231314.25910522.anemo@mba.ocn.ne.jp>
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Atsushi Nemoto wrote:
> On Mon, 11 Sep 2006 10:49:05 +0100, Thiemo Seufer <ths@networkno.de> wrote:
> > > +	tlbp
> > 
> > This needs a .set mips3/.set mips0 pair.
> 
> The TLBP is belong to MIPS I ISA, isn't it?

Uh, right. I wasn't awake when I wrote that mail. :-)

> > > +#ifdef CONFIG_CPU_MIPSR2
> > > +	_ehb			/* tlb_probe_hazard */
> > > +#else
> > > +	nop; nop; nop; nop; nop; nop	/* tlb_probe_hazard */
> > > +#endif
> > 
> > What about a mtc0_tlbp_hazard macro here?
> 
> You mean mtc0_tlbw_hazard?  I took them from tlb_probe_hazard macro in
> queue branch.

Actually, I meant an equivalent to the build_tlb_probe_entry in tlbex.c,
plus a tlb_use_hazard.

> And it looks current mtc0_tlbw_hazard asm macro does not match with
> its C equivalent ...
> 
> 	.macro	mtc0_tlbw_hazard
> 	b	. + 8
> 	.endm
> 
> #define mtc0_tlbw_hazard()						\
> 	__asm__ __volatile__(						\
> 	"	.set	noreorder				\n"	\
> 	"	nop						\n"	\
> 	"	nop						\n"	\
> 	"	nop						\n"	\
> 	"	nop						\n"	\
> 	"	nop						\n"	\
> 	"	nop						\n"	\
> 	"	.set	reorder					\n")

It also lacks a case for R2 CPUs, where IIRC _ehb is the the way
approved by the spec.


Thiemo