Re: [Qemu-devel] [PATCH] Huge TLB performance improvement

[Thiemo Seufer <ths@networkno.de>]

Paul Brook wrote:
> > > Other targets have a hardware managed TLB. On a hardware managed TLB the
> > > OS treats it as if it were infinite size, and invalidation only occurs
> > > when a OS changes the mappings. On a software managed TLB "flushes" are
> > > more likely to occur during normal operation as TLB slots are reused.
> >
> > The excessive flushing for mips happens because Qemu doesn't properly
> > model the hardware's ASID handling.
> 
> Are you sure? IIUC changing the ASID causes a full qemu TLB flush. The code 
> we're tweaking here is for single page flush.

I referred with that comment to the general problem of emulating a MMU
with ASIDs in the current qemu fremework.

> Actually that gives me an idea. When a TLB entry with a different ASID gets 
> evicted we currently flush that page. This should be a no-op because we 
> already did a full flush when the ASID changed.

That's the way the MIPS MMU is supposed to work.

> The other explanation is that the gest OS is manually doing a full TLB flush 
> by manually evicting all the TLB entries. I'd hope that a sane guest OS would 
> only do that as a last resort though.

Linux/MIPS does this only at a ASID wraparound, which doesn't happen
that often.


Thiemo