From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GmWj1-0001hq-8L for qemu-devel@nongnu.org; Tue, 21 Nov 2006 09:35:51 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GmWiz-0001eQ-Mf for qemu-devel@nongnu.org; Tue, 21 Nov 2006 09:35:50 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GmWiz-0001eB-Hc for qemu-devel@nongnu.org; Tue, 21 Nov 2006 09:35:49 -0500 Received: from [193.7.176.60] (helo=mail.bawue.net) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA:32) (Exim 4.52) id 1GmWiy-0000Vq-Hq for qemu-devel@nongnu.org; Tue, 21 Nov 2006 09:35:49 -0500 Received: from lagash (unknown [195.71.97.210]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bawue.net (Postfix) with ESMTP id 9C02DBBC18 for ; Tue, 21 Nov 2006 15:37:15 +0100 (CET) Received: from ths by lagash with local (Exim 4.63) (envelope-from ) id 1GmWjC-0003W9-H7 for qemu-devel@nongnu.org; Tue, 21 Nov 2006 14:36:02 +0000 Date: Tue, 21 Nov 2006 14:36:02 +0000 Message-ID: <20061121143602.GB12745@networkno.de> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="d6Gm4EdcadzBjdND" Content-Disposition: inline From: Thiemo Seufer Subject: [Qemu-devel] [PATCH 1/6] A cumulative MIPS patchset Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --d6Gm4EdcadzBjdND Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hello All, the attached patch is an update of Daniel's MIPS TLB improvements Thiemo --d6Gm4EdcadzBjdND Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="qemu.drow-performance" Content-Transfer-Encoding: quoted-printable Date: Sun, 12 Nov 2006 12:49:44 -0500 =46rom: Daniel Jacobowitz To: qemu-devel@nongnu.org Subject: Re: [Qemu-devel] [PATCH] Huge TLB performance improvement target-mips/cpu.h | 3 ++- target-mips/exec.h | 1 + target-mips/helper.c | 2 +- target-mips/mips-defs.h | 1 + target-mips/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++------ target-mips/translate.c | 1 + 6 files changed, 43 insertions(+), 8 deletions(-) Index: qemu-work/target-mips/cpu.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/target-mips/cpu.h 2006-11-15 22:40:28.000000000 +0000 +++ qemu-work/target-mips/cpu.h 2006-11-15 22:41:04.000000000 +0000 @@ -94,7 +94,8 @@ =09 #endif #if defined(MIPS_USES_R4K_TLB) - tlb_t tlb[MIPS_TLB_NB]; + tlb_t tlb[MIPS_TLB_MAX]; + uint32_t tlb_in_use; #endif uint32_t CP0_index; uint32_t CP0_random; Index: qemu-work/target-mips/exec.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/target-mips/exec.h 2006-11-15 22:40:28.000000000 +0000 +++ qemu-work/target-mips/exec.h 2006-11-15 22:41:04.000000000 +0000 @@ -115,5 +115,6 @@ void cpu_mips_store_count (CPUState *env, uint32_t value); void cpu_mips_store_compare (CPUState *env, uint32_t value); void cpu_mips_clock_init (CPUState *env); +void cpu_mips_tlb_flush (CPUState *env, int flush_global); =20 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */ Index: qemu-work/target-mips/helper.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/target-mips/helper.c 2006-11-15 15:13:46.000000000 +0000 +++ qemu-work/target-mips/helper.c 2006-11-15 22:41:04.000000000 +0000 @@ -46,7 +46,7 @@ tlb_t *tlb; int i, n; =20 - for (i =3D 0; i < MIPS_TLB_NB; i++) { + for (i =3D 0; i < env->tlb_in_use; i++) { tlb =3D &env->tlb[i]; /* Check ASID, virtual page number & size */ if ((tlb->G =3D=3D 1 || tlb->ASID =3D=3D ASID) && Index: qemu-work/target-mips/mips-defs.h =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/target-mips/mips-defs.h 2006-11-15 15:12:16.000000000 +0= 000 +++ qemu-work/target-mips/mips-defs.h 2006-11-15 22:41:04.000000000 +0000 @@ -22,6 +22,7 @@ /* Uses MIPS R4Kc TLB model */ #define MIPS_USES_R4K_TLB #define MIPS_TLB_NB 16 +#define MIPS_TLB_MAX 128 /* basic FPU register support */ #define MIPS_USES_FPU 1 /* Define a implementation number of 1. Index: qemu-work/target-mips/op_helper.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/target-mips/op_helper.c 2006-11-15 22:40:28.000000000 +0= 000 +++ qemu-work/target-mips/op_helper.c 2006-11-15 22:41:04.000000000 +0000 @@ -18,6 +18,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 U= SA */ #include "exec.h" +#include =20 #define MIPS_DEBUG_DISAS =20 @@ -367,7 +368,7 @@ env->CP0_EntryHi =3D val; /* If the ASID changes, flush qemu's TLB. */ if ((old & 0xFF) !=3D (val & 0xFF)) - tlb_flush (env, 1); + cpu_mips_tlb_flush (env, 1); rn =3D "EntryHi"; break; case 11: @@ -568,7 +569,14 @@ =20 /* TLB management */ #if defined(MIPS_USES_R4K_TLB) -static void invalidate_tlb (int idx) +void cpu_mips_tlb_flush (CPUState *env, int flush_global) +{ + /* Flush qemu's TLB and discard all shadowed entries. */ + tlb_flush (env, flush_global); + env->tlb_in_use =3D MIPS_TLB_NB; +} + +static void invalidate_tlb (int idx, int use_extra) { tlb_t *tlb; target_ulong addr; @@ -583,6 +591,15 @@ return; } =20 + if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) { + /* For tlbwr, we can shadow the discarded entry into + a new (fake) TLB entry, as long as the guest can not + tell that it's there. */ + memcpy (&env->tlb[env->tlb_in_use], tlb, sizeof (*tlb)); + env->tlb_in_use++; + return; + } + if (tlb->V0) { tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN); addr =3D tlb->VPN; @@ -601,6 +618,13 @@ } } =20 +static void mips_tlb_flush_extra (CPUState *env) +{ + while (env->tlb_in_use > MIPS_TLB_NB) { + invalidate_tlb(--env->tlb_in_use, 0); + } +} + static void fill_tlb (int idx) { tlb_t *tlb; @@ -627,9 +651,14 @@ =20 void do_tlbwi (void) { + /* Discard cached TLB entries. We could avoid doing this if the + tlbwi is just upgrading access permissions on the current entry; + that might be a further win. */ + mips_tlb_flush_extra (env); + /* Wildly undefined effects for CP0_index containing a too high value = and MIPS_TLB_NB not being a power of two. But so does real silicon. */ - invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1)); + invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1), 0); fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1)); } =20 @@ -637,7 +666,7 @@ { int r =3D cpu_mips_get_random(env); =20 - invalidate_tlb(r); + invalidate_tlb(r, 1); fill_tlb(r); } =20 @@ -674,8 +703,10 @@ tlb =3D &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)]; =20 /* If this will change the current ASID, flush qemu's TLB. */ - if (ASID !=3D tlb->ASID && tlb->G !=3D 1) - tlb_flush (env, 1); + if (ASID !=3D tlb->ASID) + cpu_mips_tlb_flush (env, 1); + + mips_tlb_flush_extra(env); =20 env->CP0_EntryHi =3D tlb->VPN | tlb->ASID; size =3D (tlb->end - tlb->VPN) >> 12; Index: qemu-work/target-mips/translate.c =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D --- qemu-work.orig/target-mips/translate.c 2006-11-15 22:40:28.000000000 +0= 000 +++ qemu-work/target-mips/translate.c 2006-11-15 22:41:04.000000000 +0000 @@ -2430,6 +2430,7 @@ env->PC =3D 0xBFC00000; #if defined (MIPS_USES_R4K_TLB) env->CP0_random =3D MIPS_TLB_NB - 1; + env->tlb_in_use =3D MIPS_TLB_NB; #endif env->CP0_Wired =3D 0; env->CP0_Config0 =3D MIPS_CONFIG0; --d6Gm4EdcadzBjdND--