From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Kierdelewicz Date: Tue, 28 Nov 2006 23:16:07 +0000 Subject: [LARTC] using cpu cycle counter on smp Message-Id: <20061129001607.42f5bece@localhost> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: lartc@vger.kernel.org Hi there, I was wondering if it's possible to use PSCHED_CPU (cpu cycle counter as clock source for QoS). Normally kernel menuconfig forbids it due to lack of synchronization of counters on different cpu, but: http://uwsg.iu.edu/hypermail/linux/kernel/9902.0/0053.html and quoting interesting part... ------------- checking TSC synchronization across CPUs: BIOS BUG: CPU#0 improperly initialized, has -25 usecs TSC skew! FIXED. BIOS BUG: CPU#1 improperly initialized, has 25 usecs TSC skew! FIXED. ------------- ... we can see TSC is synchronized during boot process. So, is it or is it not possible/prudent to use PSCHED_CPU on x86/x86_64, where TSCs are used? pozdrawiam, Marek Kierdelewicz _______________________________________________ LARTC mailing list LARTC@mailman.ds9a.nl http://mailman.ds9a.nl/cgi-bin/mailman/listinfo/lartc