From: Alan <alan@lxorguk.ukuu.org.uk>
To: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: jgarzik@pobox.com, linux-ide@vger.kernel.org
Subject: Re: [PATCH] pata_sl82c105: wrong assumptions about compatible PIO modes
Date: Tue, 30 Jan 2007 19:07:59 +0000 [thread overview]
Message-ID: <20070130190759.3d941365@localhost.localdomain> (raw)
In-Reply-To: <200701302040.30895.sshtylyov@ru.mvista.com>
On Tue, 30 Jan 2007 20:40:30 +0300
Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> Fix the wrong "compatible" PIO mode choices: MWDMA0 has 480 ns cycle while PIO1
> only has 383 ns cycle, and MWDMA2 timings matchs those of PIO4 exactly.
Thanks for all this review work
> Frankly speaking, I'm not sure this function is useful or correct at all --
> with the DMA timings being actually programmed in sl82c105_bmdma_start()...
It ought to be right
- bmdma_start loads the real DMA mode
- set_dmamode/set_piomode load the right PIO timings
- bmdma_stop restores the right PIO timings
> And the issue of the same registers being used for both PIO and DMA timings is
> not specific for this driver at all but seems to be addressed only by it...
For most drivers (those using the ata_timing interface) the timing merge
is done by ata_timing_compute().
> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: Alan Cox <alan@redhat.com>
next prev parent reply other threads:[~2007-01-30 18:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-01-30 17:40 [PATCH] pata_sl82c105: wrong assumptions about compatible PIO modes Sergei Shtylyov
2007-01-30 19:07 ` Alan [this message]
2007-01-30 19:08 ` Sergei Shtylyov
2007-01-30 19:27 ` Alan
2007-02-07 0:37 ` Jeff Garzik
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