From: Dave Jones <davej@redhat.com>
To: Simon Arlott <6bc04bda904655a1b91hgkso0000m4ev@thunder.lp0.eu>
Cc: Kyle McMartin <kyle@mcmartin.ca>, Mark de Vries <mark@asphyx.net>,
linux-kernel@vger.kernel.org
Subject: Re: Which CPU for VIA C7/Esther?
Date: Mon, 12 Feb 2007 18:59:07 -0500 [thread overview]
Message-ID: <20070212235907.GC13573@redhat.com> (raw)
In-Reply-To: <45D0FC66.5030205@simon.arlott.org.uk>
On Mon, Feb 12, 2007 at 11:46:46PM +0000, Simon Arlott wrote:
> MVIAC3_2 doesn't enable X86_GOOD_APIC
which is pretty irrelevant unless you have a dual C7.
> , try M686 (Pentium-Pro) - but that won't enable MMX and SSE (via -march=c3-2).
If gcc generated SSE/MMX instructions that would be a bug. (hint: it doesn't).
> These CPUs support SSE2 too...
The SSE/SSE2/SSE3 etc support for userspace is unconditional. The context switch paths will
save/restore the registers regardless of the CPU you've compiled your kernel for.
The only SSE code in the kernel is the memcpy code (which wasn't that big a win when
I last tried it on VIA due to their poor memory bandwidth), and the RAID code, which
gets tested at runtime rather than compile time.
> Also, for the C7 you'll want CRYPTO_DEV_PADLOCK_* (Hardware Crypto Devices, Support for VIA PadLock ACE) and HW_RANDOM_VIA (VIA HW Random Number Generator support).
Yes. But these aren't dependant on any CPU config options.
Dave
--
http://www.codemonkey.org.uk
prev parent reply other threads:[~2007-02-12 23:59 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-02-12 17:37 Which CPU for VIA C7/Esther? Mark de Vries
2007-02-12 19:14 ` Kyle McMartin
2007-02-12 20:16 ` Dave Jones
2007-02-12 23:46 ` Simon Arlott
2007-02-12 23:59 ` Dave Jones [this message]
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