From: "Joerg Roedel" <joerg.roedel@amd.com>
To: discuss@x86-64.org
Cc: "Andi Kleen" <ak@suse.de>, linux-kernel@vger.kernel.org
Subject: [PATCH 3/4] i386: add the X86_FEATURE_SYNC_RDTSC flag
Date: Wed, 28 Feb 2007 15:21:17 +0100 [thread overview]
Message-ID: <20070228142117.GD19452@amd.com> (raw)
In-Reply-To: <20070228140501.GA19452@amd.com>
[-- Attachment #1: Type: text/plain, Size: 337 bytes --]
From: Joerg Roedel <joerg.roedel@amd.com>
This patch adds the X86_FEATURE_SYNC_RDTSC to the i386 architecture.
This is very helpfull to simplify the get_cycles_sync() function and
remove the #ifdefs from it.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
--
Joerg Roedel
Operating System Research Center
AMD Saxony LLC & Co. KG
[-- Attachment #2: i386-x86_sync_rdtsc.patch --]
[-- Type: text/plain, Size: 1673 bytes --]
diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c
index 41cfea5..11f5730 100644
--- a/arch/i386/kernel/cpu/amd.c
+++ b/arch/i386/kernel/cpu/amd.c
@@ -241,6 +241,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (cpuid_eax(0x80000000) >= 0x80000006)
num_cache_leaves = 3;
+
+ clear_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability);
}
static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c
index 56fe265..403a495 100644
--- a/arch/i386/kernel/cpu/intel.c
+++ b/arch/i386/kernel/cpu/intel.c
@@ -188,8 +188,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
}
#endif
- if (c->x86 == 15)
+ if (c->x86 == 15) {
set_bit(X86_FEATURE_P4, c->x86_capability);
+ set_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability);
+ } else
+ clear_bit(X86_FEATURE_SYNC_RDTSC, c->x86_capability);
if (c->x86 == 6)
set_bit(X86_FEATURE_P3, c->x86_capability);
if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index 3f92b94..a9f1f01 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -75,6 +76,7 @@
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
+#define X86_FEATURE_SYNC_RDTSC (3*32+14) /* RDTSC is serializing */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
next prev parent reply other threads:[~2007-02-28 14:21 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-02-28 14:05 [PATCH 0/4] improve alternative instruction code and optimize get_cycles_sync Joerg Roedel
2007-02-28 14:14 ` [PATCH 1/4] i386: extend alternative instructions framework Joerg Roedel
2007-02-28 14:18 ` [PATCH 2/4] x86_64: changes to x86_64 architecture for alternative instruction improvements Joerg Roedel
2007-02-28 14:21 ` Joerg Roedel [this message]
2007-02-28 14:25 ` [PATCH 4/4] optimize and simplify get_cycles_sync() Joerg Roedel
2007-03-07 0:25 ` Andrew Morton
2007-03-09 9:57 ` Joerg Roedel
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